Brother International DCP 8040 Service Manual - Page 59

MFC-8440/8840D/8840DN, DCP-8040/8045D/8045DN SERVICE MANUAL 1.3 Main PCB For the entire circuit diagram of the main PCB, see APPENDIX 4.1 to 4.7 'MAIN PCB CIRCUIT DIAGRAM' in this manual. 1.3.1 CPU A Fujitsu 32bit RISC CPU, SPARClite is built in the ASIC. While the CPU is driven with a clock frequency of 66.66 MHz in the user logic block, it itself runs at 133.33 MHz, which is generated by multiplying the source clock by two. VDD3 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k R62 R54 R33 R53 R52 R51 R50 R49 R48 R29 R25 R26 R27 DATA[15-0] 6F/8F/3-6A DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] TP728 RA11 1 2 3 TP729 4 RA12 1 2 3 TP730 4 RA14 1 2 3 TP731 4 RA13 1 2 3 4 TP6 0 40 8 41 7 42 6 43 5 TP7 0 44 8 45 7 46 6 47 5 TP8 0 48 8 49 7 53 6 54 5 TP9 0 55 8 56 7 57 6 58 5 59 60 61 62 63 64 67 68 69 70 71 72 73 74 75 0V 76 TP739 U7 DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16/IO DATA17/IO DATA18/IO DATA19/IO DATA20/IO DATA21/IO DATA22/IO DATA23/IO DATA24/IO DATA25/IO DATA26/IO DATA27/IO DATA28/IO DATA29/IO DATA30/IO DATA31/IO AT-49 66.6666MHZ 0V @C88 1 C270 @X3 @C91 2 @R100 0 C2P C159 TP1000 L23 0V C103 0.68uH @R104 1M 196 VDD3 EXINTN0 C77 0V C101 TP705 @R103 0 TP5 216 RSTN 87 SCKOUT @R107 0 @U8 1 XIN 5 SSCLK 85 SCKIN Aurora 9 ADR01/24 TP35 R124 33 10 ADR02 RA7 4 0 5 11 ADR03 3 6 12 ADR04 13 TP36 2 7 ADR05 1 8 14 ADR06 RA8 0 4 5 15 ADR07 3 6 16 ADR08 17 TP37 2 7 ADR09 1 8 18 ADR10 RA9 0 4 5 19 ADR11 3 6 25 ADR12 26 TP723 2 7 ADR13 1 8 27 ADR14 RA10 4 0 5 28 ADR15/BA0 3 6 29 ADR16/BA1 30 TP724 2 7 ADR17/RASN 31 ADR18/CASN TP740 1 R129 8 0 32 ADR19/WEN TP741 R130 0 33 ADR20/DQM0 TP742 R125 0 34 TP725 R126 33 ADR21/DQM1 35 TP726 R127 33 ADR22/DQM2 36 TP727 R128 33 ADR23/DQM3 TP198 10k 10k R31 R32 211 ROMCSN0 212 ROMCSN1 213 IOWEN 214 IORDN TP10 TP11 TP12 TP13 R92 @R95 TP700 33 33 TP701 ROMCSN0 6D/7D ROMCSN1 4-7D R89 TP702 33 IOWEN R91 33 TP703 6D/4-7D IORDN 6D/7D/4-7D 95 SDCLK0 94 SDCLK1 93 SDCLK2 96 SDCKE0 97 SDCKE1 90 SDCSN0 89 SDCSN1 88 SDCSN2 92 SDSDA 91 SDSCL TP14 R81 TP15 R85 TP16 R90 TP17 R75 TP26 R78 TP29 R67 TP30 R58 TP31 R70 TP32 R72 TP33 R68 TP196 51 SDCLK0 0 7B SDCLK1 0 3-3C SDCLK2 3-3C TP722 51 0 R79 TP197 R76 51 SDCSN0 33 7A SDCSN1 33 3-2D SDCSN2 3-2D R73 4.7k 33 33 4.7k 4.7k SDCKE0 7B SDCKE1 3-3C 0V VDD3 SDSDA 3-2C SDSCL 3-2C R88 VDD3 R87 8 XOUT 6 7 TP195 FRSEL VDD VDD3 0 TP2 3 S1 0 TP3 4 S0 VSS 2 0V @C83 CY25814 C103 Fig. 3-3 R30 10k R59 10k R60 R61 10k 10k 0V ADR[1] ADR[2] ADR[3] ADR[4] ADR[5] ADR[6] ADR[7] ADR[8] ADR[9] ADR[10] ADR[11] ADR[12] ADR[13] ADR[14] ADR[15] ADR[16] ADR[17] ADR[18] ADR[19] ADR[20] ADR[21] ADR[22] ADR[23] ADR[23-1] 5F/6C/7F/3-2E/ 3-3D/4-6E/3-3C/ 7A/7B/3-2D The functions of the interface block communication with external devices are described below; 1.3.2 USB Stores the data received from the PC into DRAM as controlled by the DMA controller. The transmission speed is 480Mbps or 12Mbps. U15 Aurora Fig. 3-4 3-3