Epson FX 1170 Service Manual - Page 72

Drive Circuit, 3.7 Parallel Interface Circuit, E05A66YA, Printhead, 35VDC, IC2C1

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REV.-A 2.3.6 Printhead Drive Circuit The printhead drive circuit receives two types of signals; image data and the pulse length control signal. Image data is created in the CPU, transferred to the gate array, and latched to the printhead. The pulse length control signal is set by the CPU. The pulse length is adjusted referring to the voltage of the +35 V line. These two types of signals are sent to the printhead to print each dot. Figure 2-29 shows the printhead drive circuit. ,35VDC C P U (IC2C1) DO--7 P51 P83 GA (IC4) DO-7 Q14 HDP +35VDC t HEAD HPW HDN1 HDh9 Q2,Q4NQ6, Q8,Q9-12 Figure 2-29. Printhead Drive Circuit 2.3.7 Parallel Interface Circuit The parallel interface circuit controls the data flow from the host computer. When a STROBE signal is sent from the host computer, the data is latched into the gate array (E05A66YA). Data is transmitted until a BUSY signal is automatically sent back to the host computer to stop the data. Then the gate array outputs an IBF signal to P82 (the interrupt signal port) of the CPU. The CPU then reads the data latched into the gate array and, on completion of the reading, resets the BUSY signal to enable the host computer to send more data. Figure 2-30 shows the parallel interface circuit. Parallel l/F DO-7 STROBE BUSY - E05A66YA (IC4) DINO-7 DATAO-7 - STB ------- ~--------IB-F-- 1 1 1 1 i BUSY CPU (IC2C1) DO-7 P82 Figure 2-30. Parallel Interface Circuit 2-29

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REV.-A
2.3.6
Printhead
Drive Circuit
The
printhead
drive circuit receives two types of signals; image data and the pulse length control signal.
Image data is created in the CPU, transferred to the gate array, and latched to the
printhead.
The pulse length
control signal is set by the CPU. The pulse length is adjusted referring to the voltage of the +35 V line. These
two types of signals are sent to the
printhead
to print each dot. Figure 2-29 shows the
printhead
drive circuit.
,35VDC
CPU
(IC2C1)
DO--7
P51
P83
GA
(IC4)
DO-7
HDP
HPW
HDN1
HDh9
+35VDC
t
HEAD
Q14
Q2,Q4NQ6,
Q8,Q9-12
Figure 2-29.
Printhead
Drive Circuit
2.3.7 Parallel Interface Circuit
The parallel interface circuit controls the data flow from the host computer. When a STROBE signal is sent
from the host computer, the data is latched into the gate array (E05A66YA). Data is transmitted until a BUSY
signal is automatically sent back to the host computer to stop the data. Then the gate array outputs an
IBF
signal to
P82
(the interrupt signal port) of the CPU. The CPU then reads the data latched into the gate array
and, on completion of the reading, resets the BUSY signal to enable the host computer to send more data.
Figure 2-30 shows the parallel interface circuit.
E05A66YA
(IC4)
Parallel l/F
DO-7
STROBE
-
BUSY
-
DINO-7
DATAO-7
STB
IBF
-------
~--------
---
1
1
1
1
-
-
-
-
-
-
-
i
BUSY
CPU
(IC2C1)
DO-7
P82
Figure 2-30. Parallel Interface Circuit
2-29