Brother International HL 5030 Service Manual - Page 70
Main PCB Block Diagram, Fig. 3-2 shows the block diagram of the main PCB. HL-5030/5040/5050/5070N
View all Brother International HL 5030 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 70 highlights
CHAPTER 3 THEORY OF OPERATION 1.2 Main PCB Block Diagram Fig. 3-2 shows the block diagram of the main PCB. (HL-5030/5040/5050/5070N) A S I C Reset Circuit CPU Core (SPARClite 133MHz) BUS INT Oscillator 66.6MHz Program + Font ROM HL-5030:1MB HL-5040:4MB HL-5050/5070N:8MB Network Program (HL-5070N only)(1.5 MB) STORAGE (0.5 MB) RAM HL-5030:4MB HL-5040:8MB HL-5050/5070N:16MB RAM (DIMM) (max. 128MB) Option for HL-5040/5050/5070N EEPROM HL-5030/5040/5050:512 x 8 bit HL-5070N:8192 x 8 bit To PC or Hub To Engine PCB Network Controller (HL-5070N only) Address Decoder DRAM Control Timer FIFO CDCC Parallel I/O (HL-5040/5050/5070N only) USB I/O Oscillator 12MHz Soft Support EEPROM I/O Engine Control I/O PCI Bus Control Oscillator 25MHz (HL-5070N only) Fig. 3-2 To PC To PC 3-2