Brother International HL 5030 Service Manual - Page 71

HL-5030/5040/5050/5070N SERVICE MANUAL 1.3 Main PCB For the entire circuit diagram of the main PCB, see APPENDIX 1. to 7. 'MAIN PCB CIRCUIT DIAGRAM' in this manual. 1.3.1 CPU A Fujitsu 32bit RISC CPU, SPARClite is built in the ASIC. While the CPU is driven with a clock frequency of 66.66 MHz in the user logic block, it itself runs at 133.33 MHz, which is generated by multiplying the source clock by two. VDD3 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k R47 R39 R19 R38 R37 R36 R35 R34 R33 R15 R10 R11 R12 DATA[15-0] 7F/8F/3-6A TP731 DATA[0] DATA[1] DATA[2] DATA[3] TP732 DATA[4] DATA[5] DATA[6] DATA[7] TP733 DATA[8] DATA[9] DATA[10] DATA[11] TP734 DATA[12] DATA[13] DATA[14] DATA[15] RA12 1 2 3 4 RA13 1 2 3 4 RA15 1 2 3 4 RA14 1 2 3 4 TP6 22 40 8 41 7 42 6 43 5 TP7 22 44 8 45 7 46 6 47 5 TP8 22 48 8 49 7 53 6 54 5 TP9 22 55 8 56 7 57 6 58 5 59 60 61 62 63 64 67 68 69 70 71 72 73 74 75 0V 76 TP736 U5 DATA00 DATA01 DATA02 DATA03 DATA04 DATA05 DATA06 DATA07 DATA08 DATA09 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16/IO DATA17/IO DATA18/IO DATA19/IO DATA20/IO DATA21/IO DATA22/IO DATA23/IO DATA24/IO DATA25/IO DATA26/IO DATA27/IO DATA28/IO DATA29/IO DATA30/IO DATA31/IO VDD3 196 EXINTN0 C43 TP5 216 0V RSTN C101 AT-49 66.6666MHz 0V 0V C52 C100 C57 R70 10 X2 2 C2 C60 TP1009 L6 C103 0.82uH TP705 87 SCKOUT R71 1M 85 SCKIN Aurora 9 ADR01/24 10 ADR02 11 ADR03 12 ADR04 13 ADR05 14 ADR06 15 ADR07 16 ADR08 17 ADR09 18 ADR10 19 ADR11 25 ADR12 26 ADR13 27 ADR14 28 ADR15/BA0 29 ADR16/BA1 30 ADR17/RASN 31 ADR18/CASN 32 ADR19/WEN 33 ADR20/DQM0 34 ADR21/DQM1 35 ADR22/DQM2 36 ADR23/DQM3 TP35 TP36 TP37 TP726 TP727 TP1000 TP1001 TP1002 TP728 TP729 TP730 R90 RA8 4 3 2 1 RA9 4 3 2 1 RA10 4 3 2 1 RA11 4 3 2 1 R97 R98 R91 R92 R93 R94 33 10 5 6 7 8 10 5 6 7 8 10 5 6 7 8 10 5 6 7 8 10 10 22 33 33 33 211 TP10 R56 ROMCSN0 212 ROMCSN1 TP351 TP700 33 ROMCSN0 6D/8D 213 TP12 R49 TP702 33 IOWEN 214 TP13 R51 33 TP7036D IOWEN IORDN IORDN 6D/8D 95 SDCLK0 TP14 R63 TP196 51 SDCLK0 94 SDCLK1 93 SDCLK2 TP15 TP16 R65 R68 0 0 8B SDCLK1 3-4C SDCLK2 3-4C 96 SDCKE0 TP17 R57 51 97 SDCKE1 TP26 R61 0 TP1003 90 SDCSN0 89 SDCSN1 88 SDCSN2 92 SDSDA 91 SDSCL TP29 R42 TP197 51 SDCSN0 TP30 R41 33 8A SDCSN1 TP31 R50 33 3-2D SDCSN2 3-2D TP32 R52 33 TP33 R48 33 TP198 10k 10k 10k R16 R17 R18 0V R62 4.7k R58 4.7k R53 4.7k VDD3 SDSDA 3-2C SDSCL 3-2C Fig. 3-3 R44 10k SDCKE0 8B SDCKE1 3-4C 0V R45 10k R46 10k ADR[1] ADR[2] ADR[3] ADR[4] ADR[5] ADR[6] ADR[7] ADR[8] ADR[9] ADR[10] ADR[11] ADR[12] ADR[13] ADR[14] ADR[15] ADR[16] ADR[17] ADR[18] ADR[19] ADR[20] ADR[21] ADR[22] ADR[23] ADR[23-1] 6F/7C/7F/3-2E/ 3-4D/3-4C/8A/ 8B/3-2D 3-3