HP StorageWorks 1606 Brocade Fabric OS Troubleshooting and Diagnostics Guide v - Page 47

Segmented fabrics, Reconciling fabric parameters individually

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Segmented fabrics 3 TABLE 7 Test Switch component tests Function portLoopbackTest Performs a functional test of port N to N path. Verifies the functional components of the switch. turboRamTest Verifies that the on chip SRAM located in the 4 and 8 Gbps ASIC is using the Turbo-Ram BIST circuitry. This allows the BIST controller to perform the SRAM write and read operations at a much faster rate. Segmented fabrics Fabric segmentation is generally caused by one of the following conditions: • Incompatible fabric parameters (see "Reconciling fabric parameters individually" on page 33). • Incompatible zoning configuration (see Chapter 9, "Zone Issues"). • Domain ID conflict (see "Reconciling fabric parameters individually" on page 33). • Fabric ID conflict (see Chapter 7, "Virtual Fabrics"). • Incompatible security policies. • Incorrect fabric mode. • Incorrect policy distribution. There are a number of settings that control the overall behavior and operation of the fabric. Some of these values, such as the domain ID, are assigned automatically by the fabric and can differ from one switch to another in the fabric. Other parameters, such as the BB credit, can be changed for specific applications or operating environments, but must be the same among all switches to allow the formation of a fabric. The following fabric parameters must be identical on each switch for a fabric to merge: • R_A_TOV • E_D_TOV • Data field size • Sequence level switching • Disable device probing • Suppress class F traffic • Per-frame route priority • Long distance fabric (not necessary on Condor, GoldenEye, Condor2, or GoldenEye2 fabrics. For more information regarding these ASIC types, refer to Appendix A, "Switch Type".) • BB credit • PID format Reconciling fabric parameters individually 1. Log in to one of the segmented switches as admin. 2. Enter the configShow -pattern "fabric.ops" command. 3. Log in to another switch in the same fabric as admin. Fabric OS Troubleshoot and Diagnostics Guide 33 53-1001340-01

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Fabric OS Troubleshoot and Diagnostics Guide
33
53-1001340-01
Segmented fabrics
3
Segmented fabrics
Fabric segmentation is generally caused by one of the following conditions:
•
Incompatible fabric parameters (see
“Reconciling fabric parameters individually”
on page 33).
•
Incompatible zoning configuration (see
Chapter 9, “Zone Issues”
).
•
Domain ID conflict (see
“Reconciling fabric parameters individually”
on page 33).
•
Fabric ID conflict (see
Chapter 7, “Virtual Fabrics”
).
•
Incompatible security policies.
•
Incorrect fabric mode.
•
Incorrect policy distribution.
There are a number of settings that control the overall behavior and operation of the fabric. Some
of these values, such as the domain ID, are assigned automatically by the fabric and can differ
from one switch to another in the fabric. Other parameters, such as the BB credit, can be changed
for specific applications or operating environments, but must be the same among all switches to
allow the formation of a fabric.
The following fabric parameters must be identical on each switch for a fabric to merge:
•
R_A_TOV
•
E_D_TOV
•
Data field size
•
Sequence level switching
•
Disable device probing
•
Suppress class F traffic
•
Per-frame route priority
•
Long distance fabric (not necessary on Condor, GoldenEye, Condor2, or GoldenEye2 fabrics.
For more information regarding these ASIC types, refer to
Appendix A, “Switch Type”
.)
•
BB credit
•
PID format
Reconciling fabric parameters individually
1.
Log in to one of the segmented switches as admin.
2.
Enter the
configShow -pattern “fabric.ops”
command.
3.
Log in to another switch in the same fabric as admin.
TABLE 7
Switch component tests
Test
Function
portLoopbackTest
Performs a functional test of port N to N path. Verifies the functional components of the
switch.
turboRamTest
Verifies that the on chip SRAM located in the 4 and 8 Gbps ASIC is using the Turbo-Ram BIST
circuitry. This allows the BIST controller to perform the SRAM write and read operations at a
much faster rate.