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Hitachi HDS728080PLAT20 Specifications - Page 38

Signal definitions

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6.2 Signal definitions The pin assignments of interface signals are listed as follows: Table 18: Signal definitions PIN SIGNAL I/O Type 01 RESET- I TTL 03 DD7 I/O 3-state 05 DD6 I/O 3-state 07 DD5 I/O 3-state 09 DD4 I/O 3-state 11 DD3 I/O 3-state 13 DD2 I/O 3-state 15 DD1 I/O 3-state 17 DD0 I/O 3-state 19 GND 21 DMARQ O 3-state 23 DIOW-(*) I TTL 25 DIOR-(*) I TTL 27 IORDY-(*) O 3-state 29 DMACK- I TTL 31 INTRQ O 3-state 33 DA1 I TTL 35 DA0 I TTL 37 CS0- I TTL 39 DASP- I/O OD PIN SIGNAL I/O Type 02 GND 04 DD08 I/O 3-state 06 DD09 I/O 3-state 08 DD10 I/O 3-state 10 DD11 I/O 3-state 12 DD12 I/O 3-state 14 DD13 I/O 3-state 16 DD14 I/O 3-state 18 DD15 I/O 3-state (20) Key 22 GND 24 GND 26 GND 28 CSEL I TTL 30 GND 32 34 PDIAG- I/O OD 36 DA02 I TTL 38 CS1- I TTL 40 GND Notes: O designates an output from the drive I designates an input to the drive I/O designates an input/output common OD designates an Open-Drain output The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if the Ultra DMA transfer mode was previously chosen via Set Features. The drive becomes aware of this change upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of DMACK- at the termination of the DMA burst. Deskstar 7K80 Hard Disk Drive Specification 34

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
2.0 General features of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly	23
3.3 Actuator	23
4.0 Drive characteristics	25
4.1 Default logical drive parameters	25
4.2 Data sheet	26
4.3 World Wide Name Assignment	26
4.4 Drive organization	26
4.4.1 Drive format	26
4.4.2 Cylinder allocation	27
4.5 Performance characteristics	28
4.5.1 Command overhead	28
4.5.2 Mechanical positioning	28
4.5.3 Drive ready time	30
4.5.4 Data transfer speed	31
4.5.5 Throughput	32
4.5.6 Operating modes	33
5.0 Defect flagging strategy	35
6.0 Electrical interface specification	37
6.1 Connector location	37
6.1.1 DC power connector	37
6.1.2 AT signal connector	37
6.2 Signal definitions	38
6.3 Signal descriptions	39
6.4 Interface logic signal levels	42
6.5 Reset timings	42
6.6 PIO timings	43
6.6.1 Write DRQ interval time	43
6.6.2 Read DRQ interval time	43
6.7 Multi-word DMA timings	45
6.8 Ultra DMA timings	46
6.8.1 Initiating Read DMA	46
6.8.2 Host Pausing Read DMA	47
6.8.3 Host Terminating Read DMA	48
6.8.4 Device Terminating Read DMA	49
6.8.5 Initiating Write DMA	50
6.8.6 Device Pausing Write DMA	51
6.8.7 Device Terminating Write DMA	52
6.8.8 Host Terminating Write DMA	53
6.9 Addressing of registers	54
6.9.1 Cabling	54
7.0 Specification	57
7.1 Jumper settings	57
7.1.1 Jumper pin location	57
7.1.2 Jumper pin identification	57
7.1.3 Jumper pin assignment	58
7.1.4 Jumper positions	58
7.2 Environment	62
7.2.1 Temperature and humidity	62
7.2.2 Corrosion test	63
7.3 DC power requirements	63
7.3.1 Input voltage	63
7.3.2 Power supply current (typical)	64
7.3.3 Power supply generated ripple at drive power connector	64
7.4 Reliability	65
7.4.1 Data integrity	65
7.4.2 Cable noise interference	65
7.4.3 Start/stop cycles	65
7.4.4 Preventive maintenance	65
7.4.5 Data reliability	65
7.4.6 Required power-off sequence	65
7.5 Mechanical specifications	66
7.5.1 Physical dimensions and weight	66
7.5.2 Mounting hole locations	67
7.5.3 Connector locations	67
7.5.4 Drive mounting	68
7.5.5 Heads unload and actuator lock	68
7.6 Vibration and shock	69
7.6.1 Operating vibration	69
7.6.2 Nonoperating vibration	69
7.6.3 Operating shock	70
7.6.4 Nonoperating shock	70
7.6.5 Nonoperating rotational shock	71
7.7 Acoustics	72
7.8 Identification labels	72
7.9 Safety	73
7.9.1 UL and CSA approval	73
7.9.2 German safety mark	73
7.9.3 Flammability	73
7.9.4 Safe handling	73
7.9.5 Environment	73
7.9.6 Secondary circuit protection	73
7.10 Electromagnetic compatibility	74
7.10.1 C-TICK mark	74
7.10.2 BSMI mark	74
7.11 Packaging	74
8.0 General	75
8.1 Introduction	75
8.2 Terminology	75
8.3 Deviations from standard	75
9.0 Registers	77
9.1 Register set	77
9.2 Alternate Status Register	78
9.3 Command Register	78
9.4 Cylinder High Register	78
9.5 Cylinder Low Register	78
9.6 Data Register	79
9.7 Device Control Register	79
9.8 Drive Address Register	80
9.9 Device/Head Register	80
9.10 Error Register	81
9.11 Features Register	81
9.12 Sector Count Register	81
9.13 Sector Number Register	82
9.14 Status Register	82
10.0 General operation	85
10.1 Reset response	85
10.2 Register initialization	86
10.3 Diagnostic and Reset considerations	87
10.4 Sector Addressing Mode	88
10.4.1 Logical CHS addressing mode	88
10.4.2 LBA addressing mode	88
10.5 Power management features	89
10.5.1 Power mode	89
10.5.2 Power management commands	89
10.5.3 Standby timer	89
10.5.4 Interface capability for power modes	90
10.6 S.M.A.R.T. Function	91
10.6.1 Attributes	91
10.6.2 Attribute values	91
10.6.3 Attribute thresholds	91
10.6.4 Threshold exceeded condition	91
10.6.5 S.M.A.R.T. commands	91
10.6.6 Off-line read scanning	91
10.6.7 Error log	92
10.6.8 Self-test	92
10.7 Security Mode Feature Set	93
10.7.1 Security mode	93
10.7.2 Security level	93
10.7.3 Passwords	94
10.7.4 Operation example	94
10.7.5 Command table	98
10.8 Host Protected Area Feature	100
10.8.1 Example for operation (In LBA Mode)	100
10.8.2 Security extensions	101
10.9 Seek overlap	102
10.10 Write cache function	103
10.11 Reassign function	104
10.11.1 Auto Reassign function	104
10.12 Power-Up in Standby feature set	105
10.13 Advanced Power Management feature set (APM)	106
10.14 Automatic Acoustic Management feature set (AAM)	107
10.15 Address Offset Feature	108
10.15.1 Enable/Disable Address Offset Mode	108
10.15.2 Identify Device Data	109
10.15.3 Exceptions in Address Offset Mode	109
10.16 48-bit Address Feature Set	110
10.17 Streaming feature Set	110
10.17.1 Streaming commands	111
10.17.2 Urgent bit	111
10.17.3 Flush to Disk bit	111
10.17.4 Not Sequential bit	112
10.17.5 Read Continuous bit	112
10.17.6 Write Continuous bit	112
10.17.7 Handle Streaming Error bit	112
10.17.8 Streaming Logs	112
11.0 Command protocol	113
11.1 PIO Data In commands	113
11.2 PIO Data Out Commands	114
11.3 Non-data commands	116
11.4 DMA commands	117
12.0 Command descriptions	119
12.1 Check Power Mode (E5h/98h)	124
12.2 Configure Stream (51h)	125
12.3 Device Configuration Overlay (B1h)	127
12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h)	127
12.3.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)	127
12.3.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)	128
12.3.4 DEVICE CONFIGURATION SET (subcommand C3h)	128
12.4 Download Microcode (92h)	131
12.5 Execute Device Diagnostic (90h)	133
12.6 Flush Cache (E7h)	134
12.7 Flush Cache Ext (EAh)	135
12.8 Format Track (50h)	136
12.9 Format Unit (F7h)	138
12.10 Identify Device (ECh)	139
12.11 Idle (E3h/97h)	147
12.12 Idle Immediate (E1h/95h)	148
12.13 Initialize Device Parameters (91h)	149
12.14 Read Buffer (E4h)	150
12.15 Read DMA (C8h/C9h)	151
12.16 Read DMA Ext (25h)	153
12.17 Read Log Ext (2Fh)	155
12.17.1 General Purpose Log Directory	157
12.17.2 Extended Comprehensive SMART Error Log	158
12.17.3 Extended Self-test log sector	160
12.17.4 Read Stream Error Log	161
12.17.5 Write Stream Error Log	162
12.17.6 Streaming Performance Log	163
12.18 Read Long (22h/23h)	165
12.19 Read Multiple (C4h)	167
12.20 Read Multiple Ext (29h)	168
12.21 Read Native Max ADDRESS (F8h)	170
12.22 Read Native Max Address Ext (27h)	171
12.23 Read Sectors (20h/21h)	172
12.24 Read Sector(s) Ext (24h)	174
12.25 Read Stream DMA (2Ah)	176
12.26 Read Stream PIO (2Bh)	180
12.27 Read Verify Sectors (40h/41h)	183
12.28 Read Verify Sectors Ext (42h)	185
12.29 Recalibrate (1xh)	187
12.30 Security Disable Password (F6h)	188
12.31 Security Erase Prepare	189
12.32 Security Erase Unit (F4h)	190
12.33 Security Freeze Lock (F5h)	192
12.34 Security Set Password (F1h)	193
12.35 Security Unlock (F2h)	195
12.36 Seek (7xh)	197
12.37 Set Features (EFh)	198
12.37.1 Set Transfer mode	199
12.37.2 Write Cache	199
12.37.3 Advanced Power Management	199
12.37.4 Automatic Acoustic Management	201
12.38 Set Max ADDRESS (F9h)	202
12.38.1 Set Max Set Password (Feature=01h)	204
12.38.2 Set Max Lock (Feature=02h)	205
12.38.3 Set Max Unlock (Feature = 03h)	206
12.38.4 Set Max Freeze Lock (Feature = 04h)	207
12.39 Set Max Address Ext (37h)	208
12.40 Set Multiple (C6h)	210
12.41 Sleep (E6h/99h)	211
12.42 S.M.A.R.T. Function Set (B0h)	212
12.42.1 S.M.A.R.T. Function Subcommands	213
12.42.2 Device Attribute Data Structure	217
12.42.3 Device Attribute Thresholds data structure	220
12.42.4 S.M.A.R.T. Log Directory	222
12.42.5 S.M.A.R.T. summary error log sector	222
12.42.6 Self-test log data structure	224
12.42.7 Error reporting	225
12.43 Standby (E2h/96h)	226
12.44 Standby Immediate (E0h/94h)	228
12.45 Write Buffer (E8h)	229
12.46 Write DMA (CAh/CBh)	230
12.47 Write DMA Ext (35h)	232
12.48 Write Log Ext (3Fh)	234
12.49 Write Long (32h/33h)	235
12.50 Write Multiple (C5h)	237
12.51 Write Multiple Ext (39h)	239
12.52 Write Sectors (30h/31h)	241
12.53 Write Sectors Ext	243
12.54 Write Stream DMA (3Ah)	245
12.55 Write Stream PIO (3Bh)	247

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Deskstar 7K80 Hard Disk Drive Specification

6.2

Signal definitions

The pin assignments of interface signals are listed as follows:

Notes

The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These

lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if

the Ultra DMA transfer mode was previously chosen via Set Features. The drive becomes aware of this change

upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of

DMACK- at the termination of the DMA burst.

Table 18: Signal definitions

SIGNAL

I/O

Type

SIGNAL

I/O

Type

RESET-

TTL

GND

DD7

I/O

3–state

DD08

I/O

3–state

DD6

I/O

3–state

DD09

I/O

3–state

DD5

I/O

3–state

DD10

I/O

3–state

DD4

I/O

3–state

DD11

I/O

3–state

DD3

I/O

3–state

DD12

I/O

3–state

DD2

I/O

3–state

DD13

I/O

3–state

DD1

I/O

3–state

DD14

I/O

3–state

DD0

I/O

3–state

DD15

I/O

3–state

GND

(20)

Key

DMARQ

3–state

GND

DIOW-(*)

TTL

GND

DIOR-(*)

TTL

GND

IORDY-(*)

3–state

CSEL

TTL

DMACK-

TTL

GND

INTRQ

3–state

DA1

TTL

PDIAG-

I/O

DA0

TTL

DA02

TTL

CS0-

TTL

CS1-

TTL

DASP-

I/O

GND

designates an output from the drive

designates an input to the drive

I/O

designates an input/output common

designates an Open-Drain output