IBM DTCA-24090 Hard Drive Specifications - Page 101

DMA Data Transfer Commands

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11.4 DMA Data Transfer Commands These commands are: Identify Device DMA Read DMA Write DMA Data transfer using D M A commands differ in two ways from PIO transfers: data transfers are performed using the slave-DMA channel no intermediate sector interrupts are issued on multi-sector commands Initiation of the D M A transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command. The interrupt handler for D M A transfers is different in that: no intermediate sector interrupts are issued on multi-sector commands the host resets the DMA channel prior to reading status from the device. The DMA protocol allows high performance multi-tasking operating systems to eliminate processor overhead associated with PIO transfers. 1. Host initializes the slave-DMA channel 2. Host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder and Device/Head registers. 3. Host writes command code to the Command Register 4. The device sets D M A R Q when it is ready to transfer any part of the data. 5. Host transfers the data using the DMA transfer protocol currently in effect. 6. When all of the data has been transferred, the device generates an interrupt to the host. 7. Host resets the slave-DMA channel 8. Host reads the Status Register and, optionally, the Error Register Command Protocol 93

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11.4
DMA Data Transfer Commands
These commands are:
Identify Device DMA
Read DMA
Write DMA
Data transfer using DMA commands differ in two ways from PIO transfers:
data transfers are performed using the slave-DMA channel
no intermediate sector interrupts are issued on multi-sector commands
Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands except
that the host initializes the slave-DMA channel prior to issuing the command.
The interrupt handler for DMA transfers is different in that:
no intermediate sector interrupts are issued on multi-sector commands
the host resets the DMA channel prior to reading status from the device.
The DMA protocol allows high performance multi-tasking operating systems to eliminate processor over-
head associated with PIO transfers.
1. Host initializes the slave-DMA channel
2. Host
writes any required parameters to
the Features,
Sector Count, Sector Number, Cylinder and
Device/Head registers.
3. Host writes command code to the Command Register
4. The device sets DMARQ when it is ready to transfer any part of the data.
5. Host transfers the data using the DMA transfer protocol currently in effect.
6. When all of the data has been transferred, the device generates an interrupt to the host.
7. Host resets the slave-DMA channel
8. Host reads the Status Register and, optionally, the Error Register
Command Protocol
93