IBM DTCA-24090 Hard Drive Specifications - Page 147

PIO Flow Control Transfer Mode x

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CCH Enable reverting to power on defaults Note 1. When Feature register is 03h ( = S e t Transfer mode), the Sector Count Register specifies the transfer mechanism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. PIO Default Transfer Mode PIO Default Transfer Mode,Disable IORDY PIO Flow Control Transfer Mode x Single word DMA mode x Multiword DMA mode x Ultra DMA mode x 00000 000 00000 001 00001 nnn (nnn=000,001,010,011,100) 00010 nnn (nnn=000,001,010) 00100 nnn (nnn=000,001,010) 01000 nnn (nnn=000,001,010) Note 2. When Feature register is 05h (=Enable Adaptive mode), the Sector Count Register specifies the ABLE2 (=Adaptive battery life extender II) mode. ABLE2 support three modes. C0h - FEh ... Able mode 0 80h - BFh ... Able mode 1 60h - 7Fh ... Able mode 2 30h - 5Fh ... Able mode 2 01h - 2Fh ... Able mode 2 00h, FFh ... Aborted (Up to Active Idle) (Up to Low power Idle) (Up to Standby) ........ Performance (Up to Standby) ........ Intermediate (Up to Standby) ........ Low power When Feature register is 85h (=Disable Adaptive mode), the ABLE mode is set to 0. Note 3. If the number of auto reassigned sectors reaches the device's reassignment capacity, the write cache function will be automatically disabled. Although the device still accepts the Set Features command (with Feature register = 02h) without error, the write cache function will remain disabled. For current write cache function status, please refer to the Identify Device Information(129word) by Identify Device command. Note 4. After power on reset or hard reset, the device is set to the following features as default. Write cache Adaptive battery life extender ECC bytes Read look-ahead Reverting to power on defaults : Enable : Enable ( Able mode 1 ) : 4 bytes : Enable : Disable Command Descriptions 139

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CCH
Enable reverting to power on defaults
Note 1.
When Feature register is 03h (=Set Transfer mode), the Sector Count Register specifies the transfer mech-
anism. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value.
PIO Default Transfer Mode
00000 000
PIO Default Transfer Mode,Disable IORDY
00000 001
PIO Flow Control Transfer Mode x
00001 nnn (nnn=000,001,010,011,100)
Single word DMA mode x
00010 nnn (nnn=000,001,010)
Multiword DMA mode x
00100 nnn (nnn=000,001,010)
Ultra DMA mode x
01000 nnn (nnn=000,001,010)
Note 2.
When Feature register is 05h (=Enable Adaptive mode), the Sector Count Register specifies the ABLE2
(=Adaptive battery life extender II) mode.
ABLE2 support three modes.
C0h - FEh ... Able mode 0
(Up to Active Idle)
80h - BFh ... Able mode 1
(Up to Low power Idle)
60h - 7Fh ... Able mode 2
(Up to Standby)
........
Performance
30h - 5Fh ... Able mode 2
(Up to Standby)
........
Intermediate
01h - 2Fh ... Able mode 2
(Up to Standby)
........
Low power
00h, FFh ... Aborted
When Feature register is 85h (=Disable Adaptive mode), the ABLE mode is set to 0.
Note 3.
If the number of auto reassigned sectors reaches the device's reassignment capacity, the write cache function
will be automatically disabled.
Although the device still accepts the Set Features command (with Feature
register =
02h) without error, the write cache function will remain disabled.
For current write cache func-
tion status, please refer to the Identify Device Information(129word) by Identify Device command.
Note 4.
After power on reset or hard reset, the device is set to the following features as default.
Write cache
: Enable
Adaptive battery life extender
: Enable ( Able mode 1 )
ECC bytes
: 4 bytes
Read look-ahead
: Enable
Reverting to power on defaults
: Disable
Command Descriptions
139