IBM DTCA-24090 Hard Drive Specifications - Page 71

Data Register, Device Control Register, Drive Address Register

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9.5 Data Register This register is used to transfer data blocks between the device data buffer and the host. It is also the register through which sector information is transferred on a Format Track command, and configuration information is transferred on an Identify Device command. All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO only. The register contains valid data only when D R Q = 1 in the Status Register. 9.6 Device Control Register Device Control Register 7 6 5 4 3 2 1 0 1 SRST IEN 0 Figure 39. Device Control Register Bit Definitions SRST (RST) -IEN Software Reset. The device is held reset when R S T = 1 . Setting R S T = 0 re-enables the device. The host must set R S T = 1 and wait for at least 5 microseconds before setting R S T = 0 , to ensure that the device recognizes the reset. Interrupt Enable. When I E N = 0 , and the device is selected, device interrupts to the host will be enabled. When I E N = 1 , or the device is not selected, device interrupts to the host will be disabled. 9.7 Drive Address Register Drive Address Register 7 6 5 4 3 2 1 0 HIZ WTG H3 H2 H1 H0 DS1 DS0 Figure 40. Drive Address Register This register contains the inverted drive select and head select addresses of the currently selected drive. Bit Definitions HIZ High Impedance. This bit is not device and will always be in a high impedance state. -WTG -Write Gate. This bit is 0 when writing to the disk device is in progress. -H3,-H2,-H1,-H0 -Head Select. These four bits are the one's complement of the binary coded address of the currently selected head. -H0 is the least significant. Registers 63

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9.5
Data Register
This register is used to transfer data blocks between the device data buffer and the host.
It is also the register
through which sector information is transferred on a Format Track command, and configuration information
is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide.
Data transfers are
PIO only.
The register contains valid data only when DRQ=1 in the Status Register.
9.6
Device Control Register
Device Control Register
7
6
5
4
3
2
1
0
1
SRST
IEN
0
Figure 39. Device Control Register
Bit Definitions
SRST (RST)
Software Reset.
The device is held reset when RST=1.
Setting R S T = 0 re-enables
the device.
The
host must
set RST=1
and wait for at
least 5 microseconds
before setting
RST=0, to ensure that the device recognizes the reset.
-IEN
Interrupt Enable.
When IEN=0, and the device is selected, device interrupts to the
host will be enabled.
When IEN=1, or the device is not selected, device interrupts to
the host will be disabled.
9.7
Drive Address Register
Drive Address Register
7
6
5
4
3
2
1
0
HIZ
WTG
H3
H2
H1
H0
DS1
DS0
Figure 40. Drive Address Register
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ
High Impedance.
This bit is not device and will always be in a high impedance state.
-WTG
-Write Gate.
This bit is 0 when writing to the disk device is in progress.
-H3,-H2,-H1,-H0
-Head Select.
These four bits are the one's complement of the binary coded address
of the currently selected head. -H0 is the least significant.
Registers
63