IBM DTCA-24090 Hard Drive Specifications - Page 49

PIO Timings

Page 49 highlights

6.5 PIO Timings The PIO cycle timings meet Mode 4 of the ATA-3 description. HCS0, HCS1 +HA0 2 HIOR, HIOW < T1 > < < < T9 > T0 > T2 > < T2I > Write data +HD00 15 < T3 > < T4 > Read data +HD00 15 HIOCS16 +HIORDY > T7 < < T5 > T6Z < T6 > T8 < < TA > > TRD < < TB > PARAMETER DESCRIPTION MIN MAX Note (nsec) (nsec) T0 Cycle time 120 T1 HCS0 1, +HA00 02 valid to HIOR, HIOW active 25 T2 HIOR, HIOW pulse width 70 T2I HIOR, HIOW recovery 25 T3 +HD00 15 setup to HIOW high 20 T4 HIOW high to +HD00 15 hold 10 T5 +HD00 15 setup to HIOR high 20 *1 T6 HIOR high to +HD00 15 hold 5 T6Z HIOR high to +HDOO 15 tristate 30 T7 HCS0 1, +HA00 02 valid to HIOCS16 assertion 30 T8 HCS0 1, +HA00 02 invalid to HIOCS16 negation 30 T9 HIOR, HIOW high to HCS0 1, +HA00 02 hold 10 TRD Read data valid to +HIORDY active 0 TA HIOR, HIOW low to +HIORDY low 35 TB +HIORDY pulse width 1250 Note *1 : This value is applied only when +HIORDY is not negated. When +HIORDY is negated, TRD is applied. Figure 24. PIO cycle timings Electrical Interface Specifications 41

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6.5
PIO Timings
The PIO cycle timings meet Mode 4 of the ATA-3 description.
HCS0, HCS1
+HA0 2
<
T9
>
<
T1 > <
T0
>
HIOR, HIOW
<
T2
><
T2I
>
Write data
+HD00 15
<
T3
> < T4 >
Read data
+HD00 15
<
T5
> T6Z <
>
T7
<
T6
> T8 <
HIOCS16
< TA
>
> TRD <
+HIORDY
<
TB
>
MIN
MAX
Note
PARAMETER DESCRIPTION
(nsec) (nsec)
T0
Cycle time
120
T1
HCS0 1, +HA00 02 valid to
HIOR, HIOW active
25
T2
HIOR, HIOW pulse width
70
T2I
HIOR, HIOW recovery
25
T3
+HD00 15 setup to
HIOW high
20
T4
HIOW high to +HD00 15 hold
10
T5
+HD00 15 setup to
HIOR high
20
*1
T6
HIOR high to +HD00 15 hold
5
T6Z
HIOR high to +HDOO 15 tristate
30
T7
HCS0 1, +HA00 02 valid to
HIOCS16 assertion
30
T8
HCS0 1, +HA00 02 invalid to
HIOCS16 negation
30
T9
HIOR, HIOW high to
HCS0 1, +HA00 02 hold
10
TRD
Read data valid to +HIORDY active
0
TA
HIOR, HIOW low to +HIORDY low
35
TB
+HIORDY pulse width
1250
Note *1 : This value is applied only when +HIORDY is not negated. When +HIORDY
is negated, TRD is applied.
Figure 24. PIO cycle timings
Electrical Interface Specifications
41