Intel S2600IP Service Guide - Page 94

BIOS Setup Utilities Option Values: Enabled Disabled Help Text: The next cache line will be prefetched into L1 data cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. [Disabled] - Only fetches cache line with data required by the processor (64 bytes). Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 Data Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. 30. DCU Instruction Prefetcher Option Values: Enabled Disabled Help Text: The next cache line will be prefetched into L1 instruction cache from L2 or system memory during unused cycles if it sees that the processor core has accessed several bytes sequentially in a cache line as data. Comments: DCU Data Prefetcher is normally Enabled, for best efficiency in L1 I Cache and Memory Channel use, but disabling it may improve performance for some processing loads and on certain benchmarks. 31. Direct Cache Access (DCA) Option Values: Enabled Disabled Help Text: Allows processors to increase the I/O performance by placing data from I/O devices directly into the processor cache. Comments: System performance is usually best with Direct Cache Access Enabled. In certain unusual cases, disabling this may give improved results. 32. SMM Wait Timeout Option Values: [Entry Field 20 - 3000ms, 20 is default] Help Text: Millisecond timeout waiting for BSP and APs to enter SMM. Range is 20ms to 3000ms. Comments: Amount of time to allow for the SMI Handler to respond to an SMI. If exceeded, BMC generates an SMI Timeout and resets the system. Note: This field is temporary, and will be removed when no longer required. 82 Intel® Server System R2000IP Service Guide