ZyXEL U-1496S Plus User Guide - Page 49
Special MNP compatibility See also &Kn, S27b0, S38b5.
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S39 Bit-mapped register, default = 000 (7) =0; Does not include resync information in recorded voice data. =1; Includes resync information in recorded ADPCM file. Note: When the resync function is enabled, the modem sends a resync symbol (hex 10 and 12) every 50 ms. ADPCM data can be edited without losing sync if enabled. mode. received. (6) =0; DTMF detection is enabled only in voice PLAY or RECORD =1; DTMF detection is enabled when command "AT+VLS=2" is Note: AT auto baud detection is disabled when DTMF detection is enabled. (5) =1; Disables scrambler/descrambler in V.26bis mode. Enables compatibility with older modems which have no V.25bis scrambler/descrambler unit. (4) =1; Class 2 fax with DTE speed shifting; +FCON at current DTE rate and shift to 19200 at next phase (3) =1; Class 2 fax with Bitfax compatibility; +FCON at 2400 and shift to 19200 at next phase. (2) =1; Reverse Answer; answer in originate mode. (1,0) Reserved. S40 Bit-mapped register, default = 000 (7) Reserved. (6) =1; Enable type 4 ring detection. (5) =1; Enable type 3 ring detection. (4) =1; Enable type 2 ring detection. (3) =1; Enable type 1 ring detection. (2) =1; Enable caller ID detection. (See also S24b2, *T) Q2 (1) =1; ATQ2, modem does not return result code in answering. No RING or CONNECT message. (0) Reserved. Note: Bits (6,5,4,3) enable ring detection on a combination of four ring types. All 0's enable ring detection on any ring longer than 100ms. S41 Bit-mapped register, default = 000 (7) =1; Ignore calling tone. Not to be used as fax detection. (6) =1; Do not answer on the first ring, force S0=2. (5) =1; DSR follows DCD, off for 0.5 sec on DCD on-off transition. (See &Sn). (4) =1; In X2-X7 setting, modem waits for S6 seconds before dialing and ignores dial tone detection. (3) =1; Enable CCITT signals 140 and 141 on EIA-232D interface. (2) =1; Extend the retrain time-out timer to 5 minutes. (See *Qn, S27b6). (1) =0; Flag idle in V.25bis HDLC. (See *I1, S17b6) =1; Mark idle in V.25bis HDLC. (0) =1; Special MNP compatibility (See also &Kn, S27b0, S38b5). S42 Bit-mapped register, default = 000 (7) =1; DCD pulses off for 0.5 sec at carrier loss, always on otherwise.