ZyXEL U-1496S Plus User Guide - Page 56
DSR according to CCITT. If S44b4=1, DSR follows DTR.
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&N43 CELL &N44CELL &N45 CELL &N46 CELL &N47 CELL &N48 CELL &N49 CELL 12000 9600 7200 4800T 4800C 3866C 2400C Note: All speeds over 9600 bps are trellis coded except V.29; V.32bis 7200 is also trellis coded. Not all modes available in all models. Check the compatibility table. All ZyXEL modes except ZyXEL 16800 are available only with Plus models. + &P0 Pulse dial make/break ratio= 39%/61% (Default). &P1 Pulse dial make/break ratio= 33%/67%. &R0 CTS tracks RTS, response delay is set in S26. + &R1 Modem assumes RTS always ON, ignores the changes (Default). (&Rn controls the synchronous mode operation only, in asynchronous mode RCTS/RTS are used for flow control.) + &S0 Modem forces DSR always ON (Default). &S1 DSR according to CCITT. If S44b4=1, DSR follows DTR. If S41b5=1, DSR always on but follows DCD off for 0.5 second. &T0 Terminate test in progress. &T1 Initiate Analog LoopBack (ALB) test. &T2 Reserved. &T3 Initiate Local Digital Loopback (LDL) test. &T4 Grant Remote Digital Loopback request from remote modem. &T5 Deny Remote Digital Loopback request from remote modem (Default). &T6 Initiate Remote Digital Loopback (RDL) test. &T7 Initiate Remote Digital Loopback with self test (RDL + ST). &T8 Initiate Analog LoopBack with self test (ALB+ST). &V0 View current active settings. &V1 View user profile 0 settings. &V2 View user profile 1 settings. &V3 View user profile 2 settings. &V4 View user profile 3 settings. &V5 View factory default settings. &W0 &W1 &W2 &W3 Save current settings to user profile 0. (See also S35b6). Save current settings to user profile 1. Save current settings to user profile 2. Save current settings to user profile 3. + &X0 Modem provides synchronous transmit clock signal (Internal clock to pin 15 of EIA-232D) (Default). &X1 Terminal provides synchronous transmit clock signal (External clock, from pin 24 of EIA-232D). &X2 Receiving carrier provides synchronous transmit clock signal (Remote or Slave clock, to pin 15 of EIA-232D). &Y0 Destructive break, expedited. (Destructive break clears the buffer, expedited