AMD AMD-K6-2/450 Design Guide
AMD AMD-K6-2/450 - MHz Processor Manual
 |
View all AMD AMD-K6-2/450 manuals
Add to My Manuals
Save this manual to your list of manuals |
AMD AMD-K6-2/450 manual content summary:
- AMD AMD-K6-2/450 | Design Guide - Page 1
® Embedded AMD-K6™ Processors BIOS Design Guide Application Note Publication # 23913 Rev: A Issue Date: November 2000 Amendment/0 - AMD AMD-K6-2/450 | Design Guide - Page 2
this publication. Except as set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, AMD, the AMD logo, and combinations thereof, AMD-K6, 3DNow!, E86, AMD PowerNow!, and Super7 are trademarks, and FusionE86 is a service mark of Advanced Micro Devices, Inc. MMX - AMD AMD-K6-2/450 | Design Guide - Page 3
1 Audience 1 Processor Models and Steppings 2 AMD-K6™E Embedded Processor 3 AMD-K6™-2 Processor 3 AMD-K6™-2E Embedded Processor 4 AMD-K6™-2E+ Embedded Processor 4 AMD-K6™-III Processor 5 AMD-K6™-IIIE+ Embedded Processor 5 BIOS Consideration Checklist 6 CPUID 6 CPU Speed Detection 6 Model - AMD AMD-K6-2/450 | Design Guide - Page 4
Support 64 Detection Algorithm for Determining Instruction Set Support 65 AMD Processor Signature (Extended Function 66 Displaying the Processor's Name 66 Displaying Cache Information 67 Determining AMD PowerNow!™ Technology Information . . 67 Sample Code 67 New AMD-K6™ Processor Instructions - AMD AMD-K6-2/450 | Design Guide - Page 5
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Software Timing Dependencies Relative to Memory Controller Setup 69 Pipelining Support 69 Read-Only Memory 70 Appendix A 71 CPUID 71 Standard Functions 72 Extended Functions 75 Cache Associativity - AMD AMD-K6-2/450 | Design Guide - Page 6
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 vi Contents - AMD AMD-K6-2/450 | Design Guide - Page 7
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide List of Figures Figure 1. CPUID Instruction Flow Chart 12 Figure 2. Extended Feature Enable Register (EFER) (Models 7 and 8/[7:0 18 Figure 3. Write Handling Control Register (WHCR) (Models 7 and 8/[7:0 - AMD AMD-K6-2/450 | Design Guide - Page 8
AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Figure 20. L2 Tag or Data Location (AMD-K6™-2E+ Processor)-EDX 50 Figure 21. L2 Tag or Data Location (AMD-K6™-IIIE+ Processor)-EDX 50 Figure 22. L2 Data-EAX (same as Figure 14 51 Figure 23. L2 Tag Information (AMD-K6™-2E+ Processor - AMD AMD-K6-2/450 | Design Guide - Page 9
AMD-K6™ Processor Family 2 Table 2. AMD-K6™E Processor (Model 7) and AMD-K6™ Processor (Model 8/[7:0]) State after RESET 8 Table 3. AMD-K6™ Processor (Model 8/[F:8]) and AMD-K6™-2E Processor (Model 8/[F:8]) State after RESET 8 Table 4. AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and AMD-K6 - AMD AMD-K6-2/450 | Design Guide - Page 10
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Table 18. Processor-to-Bus Clock Ratios (Model Standard-Power D 35 Table 19. Model-Specific Registers Supported by Model 9 38 Table 20. Extended Feature Enable Register (EFER) Definition (Models 9 and D - AMD AMD-K6-2/450 | Design Guide - Page 11
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Revision History Date November 2000 Rev Description A Initial public release. Revision History xi - AMD AMD-K6-2/450 | Design Guide - Page 12
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 xii Revision History - AMD AMD-K6-2/450 | Design Guide - Page 13
support the AMD-K6™ processors used by AMD's embedded customers. The information in this application note pertains to the following processors in the AMD-K6 family: s AMD-K6E embedded processor s AMD-K6-2 processor s AMD-K6-2E embedded processor s AMD-K6-2E+ embedded processor s AMD-K6-III processor - AMD AMD-K6-2/450 | Design Guide - Page 14
of the AMD-K6 processor family. Table 1. Features of the AMD-K6™ Processor Family Processor AMD-K6E AMD-K6-2 AMD-K6-2 and AMD-K6-2E AMD-K6-2E+ AMD-K6-III AMD-K6-IIIE+ Model/ Process (in Number 3DNow!™ 3DNow! AMD PowerNow!™ Stepping microns) of MSRs1 Instructions Extensions Technology 7 0.25 - AMD AMD-K6-2/450 | Design Guide - Page 15
in the 0.25-micron process. s Model 7 supports six model-specific registers (MSRs). AMD-K6™-2 Processor Model 8/[7:0] Model 8/[F:8] Some important features supported by the AMD-K6-2 processor include the 3DNow!™ instruction set and a 100-MHz processor bus. Model 8/[7:0] is any of eight possible - AMD AMD-K6-2/450 | Design Guide - Page 16
In addition to supporting the 3DNow! instruction set and a 100MHz processor bus, the AMD-K6-2E+ processor contains a 128Kbyte backside L2 cache. It also supports the 3DNow! DSP instructions extensions. Low-power versions of the processor support AMD PowerNow!™ technology. Model D/[7:4] is any - AMD AMD-K6-2/450 | Design Guide - Page 17
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide AMD-K6™-III Processor Model 9/[3:0] In addition to supporting the 3DNow! instruction set and a 100MHz processor bus, the AMD-K6-III processor contains a 256Kbyte backside L2 cache. Model 9/[3:0] is any - AMD AMD-K6-2/450 | Design Guide - Page 18
is implemented differently in models 8/[F:8], 9, and D. s For the AMD-K6-2E, AMD-K6-2E+, AMD-K6-III, and AMD-K6-IIIE+ processors, utilize the information provided in the Processor State Observability Register (PSOR) to display the correct processor bus frequency. 6 BIOS Consideration Checklist - AMD AMD-K6-2/450 | Design Guide - Page 19
/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Cache Testing SMM Issues s The AMD-K6 family of processors does not contain MSRs to allow for testing of the L1 cache. However, the AMD-K6-2E+, AMD-K6-III, and AMD-K6-IIIE+ processors do contain an MSR that - AMD AMD-K6-2/450 | Design Guide - Page 20
Embedded AMD-K6™ Processors BIOS Design Guide States after RESET and INIT 23913A/0-November 2000 Register States after RESET and INIT After the processor has completed its initialization following the recognition of an asserted RESET or INIT signal, the states of all architecture registers - AMD AMD-K6-2/450 | Design Guide - Page 21
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Table 4. AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and AMD-K6™-IIIE+ Processors (Model D) State after RESET Register EDX EFER2 L2AAR PFIR PSOR STAR UWCCR WHCR EPMR4 RESET State 0000_05MSh1 - AMD AMD-K6-2/450 | Design Guide - Page 22
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Built-In Self-Test (BIST) Fo r a l l m o d e l s o f t h e A M D -K following: s L1 instruction and data caches s L2 unified cache (models 9 and D only) s Instruction and data translation lookaside buffers - AMD AMD-K6-2/450 | Design Guide - Page 23
these steppings. For example, a BIOS boot string for a Model 9, stepping 3, 450MHz AMD-K6-III processor would look like this: s AMD-K6(tm)-III/450 Figure 1 on page 12 shows a flow chart for the CPUID instruction. Use this chart to implement a CPUID algorithm. CPUID Identification Algorithms 11 - AMD AMD-K6-2/450 | Design Guide - Page 24
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Check for CPUID instruction support CPUID instruction No supported No CPUID instruction-Use other means to detect CPU type Yes Execute CPUID Standard Function EAX=0 Store Vendor String No EAX > 1 ? - AMD AMD-K6-2/450 | Design Guide - Page 25
has the IDT base located at offset FF94h. I/O Trap Dword Differences The I/O trap dword is located at offset FFA4h. Its AMD-K6 processor bit fields are shown in Table 6. This state-save area, which is reserved in Pentium processors, contains information regarding an I/O instruction that may have - AMD AMD-K6-2/450 | Design Guide - Page 26
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Model-Specific Registers Overview Each of the models of the AMD-K6 processor family support a different set of model-specific registers (MSRs). These differences are summarized by register in Table 7. The - AMD AMD-K6-2/450 | Design Guide - Page 27
AMD-K6 family of processors support identically-MCAR, MCTR, TR12, and TSC. 2. L2D, EWBEC, and DPE are bits/fields supported in EFER for the indicated models/steppings. All models/steppings support the System Call Extension (SCE) bit in EFER, even if the corresponding SYSCALL and SYSRET instructions - AMD AMD-K6-2/450 | Design Guide - Page 28
™ Processors BIOS Design Guide 23913A/0-November 2000 Standard Model-Specific Registers (All Models) Machine-Check Address Register (MCAR) and Machine-Check Type Register (MCTR) This section describes the four standard MSRs that every model and stepping of the AMD-K6 family of processors support - AMD AMD-K6-2/450 | Design Guide - Page 29
Model 8/[7:0] Registers The AMD-K6E processor Model 7 and the AMD-K6-2 processor Model 8/[7:0] provide the model-specific registers listed in Table 9. The contents of ECX selects the MSR to be addressed by the RDMSR and WRMSR instruction. Table 9. Model-Specific Registers Supported by Models 7 and - AMD AMD-K6-2/450 | Design Guide - Page 30
Function R Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. Notes: 1. The AMD-K6E processor Model 7 provides the SCE bit in the EFER register - AMD AMD-K6-2/450 | Design Guide - Page 31
November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Write Handling Control Register (WHCR AMD-K6 processors contain a split level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set - AMD AMD-K6-2/450 | Design Guide - Page 32
Support" on page 69 for more information on the WCDE bit. Write Allocate Enable Limit Field The WAELIM field is 7 bits wide. This field, multiplied AMD-K6 or AMD-K6E processor data sheet. The maximum value of this limit is ((27-1) · 4 Mbytes) = 508 Mbytes. When all the bits in this field are set - AMD AMD-K6-2/450 | Design Guide - Page 33
Information Embedded AMD-K6™ Processors BIOS Design Guide Write Allocate Enable 15-to-16-Mbyte Field. This value (8), when multiplied by 4 system contains one of these peripherals, the bit should be set to 0 (even if the WAE15M bit is set to 0, write allocates can still occur between 15 Mbytes and - AMD AMD-K6-2/450 | Design Guide - Page 34
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 SYSCALL/SYSRET Target Address Register (STAR) Models 8, 9, and D implement the STAR register. This register contains the target EIP address used by the SYSCALL instruction and the 16-bit code and stack segment selector bases used - AMD AMD-K6-2/450 | Design Guide - Page 35
BIOS Design Guide Model 8/[F:8] Registers The AMD-K6-2 processor Model 8/[F:8] and AMD-K6-2E processor Model 8/[F:8] provides the ten MSRs listed in Table 12. The contents of ECX select the MSR to be addressed by the RDMSR and WRMSR instruction. Table 12. Model-Specific Registers Supported by - AMD AMD-K6-2/450 | Design Guide - Page 36
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Extended Feature Enable Register (EFER) The Extended Feature Enable Register (EFER) contains the control bits that enable the extended features of the processor. Figure 5 shows the format of the EFER - AMD AMD-K6-2/450 | Design Guide - Page 37
Embedded AMD-K6™ Processors BIOS Design Guide buffer operates in conjunction with the Memory Type Range Registers (MTRRs). Refer to "UC/WC Cacheability Control Register (UWCCR)" on page 30 for a description of the MTRRs. Merging multiple write cycles into a single write cycle reduces processor bus - AMD AMD-K6-2/450 | Design Guide - Page 38
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 samples the EWBE# signal. If EWBE# is sampled negated, the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until EWBE# is sampled asserted. This setting provides - AMD AMD-K6-2/450 | Design Guide - Page 39
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Write Handling Control Register (WHCR AMD-K6 processors contain a split level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set - AMD AMD-K6-2/450 | Design Guide - Page 40
AMD-K6™ Processors BIOS Design Guide AMD-K6 or AMD-K6E processor data sheet. The maximum value of this limit is ((210-1) · 4 Mbytes) = 4092 Mbytes. When all the bits in this field are set Mbytes of RAM would program the WAELIM field with t he value 00_0000_1000b. This value (8), when multiplied by 4 - AMD AMD-K6-2/450 | Design Guide - Page 41
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Write Allocate Enable 15-to-16-Mbyte Field The WAE15M bit is used to enable write allocations for the memory write cycles that address the 1 Mbyte of memory between 15 Mbytes and 16 Mbytes. This bit must be set to 1 to allow - AMD AMD-K6-2/450 | Design Guide - Page 42
Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November processor's cache, then flush the cache. This can be achieved by setting the CD bit in CR0 to 1 and executing the WBINVD instruction. Following the programming of the UWCCR, the processor's cache must be enabled by setting - AMD AMD-K6-2/450 | Design Guide - Page 43
/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Symbol Description Bits UC1 Uncacheable Mask & Physical Base Address = Mask & Physical Address Generated then, the physical address generated by the processor is in the range. WCn (n=0, 1) When set to 1, this - AMD AMD-K6-2/450 | Design Guide - Page 44
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Memory-Range Restrictions The following rules regarding the address alignment and size of each range must be adhered to when programming the physical base address and physical address mask fields of the - AMD AMD-K6-2/450 | Design Guide - Page 45
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Examples Suppose that set to 0, and bit 0 of the UWCCR register is set to 1 (UC0). s Extracting the 15 most-significant bits of the 32-bit physical base address that corresponds to 1 Gbyte (4000_0000h) yields a physical base - AMD AMD-K6-2/450 | Design Guide - Page 46
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Processor State Observability Register (PSOR) Models 8/[F:8], 9, and standard-power versions of Model D provide the Processor State Observability Register (PSOR) as defined in Figure 8. The PSOR register - AMD AMD-K6-2/450 | Design Guide - Page 47
AMD-K6™ Processors BIOS Design Guide Table 17. Processor-to-Bus Clock Ratios (Models 8/[F:8] and 9) State of BF[2:0] Processor-Clock to Bus-Clock Ratio 100b 2.5x 101b 3.0x 110b 6.0x1 111b 3.5x 000b 4.5x 001b 5.0x 010b 4.0x 011b 5.5x Notes: 1. The 2.0x ratio that is supported - AMD AMD-K6-2/450 | Design Guide - Page 48
Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November When the PFIR is written to (using the WRMSR instruction), the invalidation and, optionally, the flushing begins. invalidate or flush a page results in a page fault, the processor sets the PF bit to 1, and the invalidate or - AMD AMD-K6-2/450 | Design Guide - Page 49
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide F/I Bit This bit is used to control the type of action that occurs to the specified linear page. If a 0 is written to this bit, the - AMD AMD-K6-2/450 | Design Guide - Page 50
selects the MSR to be addressed by the RDMSR and WRMSR instruction. The AMD-K6-III processor contains a split Level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The cache line size is 32 bytes, and lines - AMD AMD-K6-2/450 | Design Guide - Page 51
2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Extended Feature Enable set to 1 to enable usage of the SYSCALL and SYSRET instructions. Note: Setting L2D to 1 does not guarantee cache coherency. To ensure coherency, the processor's caches must be disabled (by setting - AMD AMD-K6-2/450 | Design Guide - Page 52
MESI Line0/MESI Tag/LRU Way 0 Way 1 Way 2 Way 3 1024 sets Set 1023 Figure 11. L2 Cache Organization (AMD-K6™-III Processor) The L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed-RDMSR or WRMSR-and the contents of the EDX - AMD AMD-K6-2/450 | Design Guide - Page 53
w o r d Reserved Symbol Description Bit Set Selects the desired cache set 15-6 Line Selects Line1 (1) or Line0 (0) 5 Octet Selects one of four octets 4-3 Dword Selects upper (1) or lower (0) dword 2 Figure 13. L2 Tag or Data Location (AMD-K6™-III Processor)-EDX Model 9 Registers 41 - AMD AMD-K6-2/450 | Design Guide - Page 54
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Table 21. Tag versus Data Selector Instruction T/D (EDX[20]) Operation RDMSR 0 Read dword from L2 data array into EAX. Dword location is specified by EDX. RDMSR 1 Read tag, line state and LRU - AMD AMD-K6-2/450 | Design Guide - Page 55
Figure 15. L2 Tag Information (AMD-K6™-III Processor)-EAX LRU (Least Recently Used) Field For the 4-way set associative L2 cache, each way support the 256-Kbyte L2 cache on the AMD-K6-III processor is 16 bits, which corresponds to bits 31:16 of the EAX register. However, the AMD-K6-III processor - AMD AMD-K6-2/450 | Design Guide - Page 56
and Figure 15 on page 43). It is important to note that this special consideration is only required if the AMD-K6-III processor will subsequently be expected to properly execute instructions or access data from the L2 cache following the setup of the L2 cache by means of the L2AAR register. If the - AMD AMD-K6-2/450 | Design Guide - Page 57
MSR to be addressed by the RDMSR and WRMSR instruction. The AMD-K6-2E+ and AMD-K6-IIIE+ processors contain a split Level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The cache line size is 32 bytes, and - AMD AMD-K6-2/450 | Design Guide - Page 58
the AMD-K6-2E+ and AMD-K6-IIIE+ processors provide the Processor State Observability Register (PSOR) as defined in Figure 17. Note: Standard-power versions of Model D support the PSOR as defined on page 34. The PSOR register is MSR C000_0087h. . Symbol Description Bits PBF Pin Bus Frequency - AMD AMD-K6-2/450 | Design Guide - Page 59
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide NOL2 Bit STEP Field EBF[2:0] Field This read-only bit indicates whether the processor contains an L2 cache. Note: This bit is always set to 0 for Model D. This read-only field contains the stepping ID. - AMD AMD-K6-2/450 | Design Guide - Page 60
+ and AMD-K6-IIIE+ processors. The L2 cache in the AMD-K6-2E+ and AMD-K6-IIIE+ processors is organized as shown in Figure 18: s Four 32-Kbyte ways (AMD-K6-2E+ processor) or four 64Kbyte ways (AMD-K6-IIIE+ processor) s Each way contains 512 (AMD-K6-2E+ processor) or 1024 (AMD-K6-IIIE+ processor) sets - AMD AMD-K6-2/450 | Design Guide - Page 61
AMD-K6-2E+ because there are half as many sets implemented on the AMD-K6-2E+ (512 sets) as the AMD-K6-IIIE+ processor (1024 sets). Bit 20 of EDX (T/D) determines whether the access is to the L2 cache data or tag. Table 24 on page 51 describes the operation that is performed based on the instruction - AMD AMD-K6-2/450 | Design Guide - Page 62
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Symbol Description T/D Selects Tag (1) or Data (0) access Way Selects desired cache way Bit 20 17-16 31 21 20 19 18 17 16 15 14 T / Way Set D Reserved Symbol Description Bit Set Selects the desired cache set 14 - AMD AMD-K6-2/450 | Design Guide - Page 63
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Table 24. Tag versus Data Selector (same as Table 21) Instruction T/D (EDX[20]) Operation RDMSR 0 Read dword from L2 data array into EAX. Dword location is specified by EDX. RDMSR 1 Read tag, line - AMD AMD-K6-2/450 | Design Guide - Page 64
AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 31 Tag 14 13 12 11 10 9 8 7 Line1ST Line0ST 0 C LRU M D Reserved Symbol Description Bit Tag Tag data L2 Tag Information (AMD-K6™-IIIE+ Processor)-EAX LRU (Least Recently Used) Field For the 4-way set associative L2 cache, each - AMD AMD-K6-2/450 | Design Guide - Page 65
support the 256-Kbyte L2 cache on the AMD-K6-III and AMD-K6-IIIE+ is 16 bits, which corresponds to bits 31:16 of the EAX register. However, the AMD-K6-IIIE+ processor required if the AMD-K6-IIIE+ processor will subsequently be expected to properly execute instructions or access data from the L2 - AMD AMD-K6-2/450 | Design Guide - Page 66
BIOS Design Guide 23913A/0-November 2000 Enhanced Power Management Register (EPMR) (Low-Power Versions) To support AMD PowerNow! technology, the low-power versions of the AMD-K6-2E+ and AMD-K6-IIIE+ processors Model D are designed with enhanced power management (EPM) features: dynamic bus divisor - AMD AMD-K6-2/450 | Design Guide - Page 67
AMD-K6™ Processors BIOS Design Guide EPM 16-Byte I/O Block (Low-Power Versions Only) The EPM 16-byte I/O block contains one 4-byte field-Bus field for altering the core voltage and frequency settings. Systeminitiated inquire (snoop) cycles are not supported and must be prevented during EPM Stop - AMD AMD-K6-2/450 | Design Guide - Page 68
Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 31 12 11 10 9 8 7 54 0 BV SGTC V C I D BDC IBF[2:0] VIDO MC Symbol SGTC BVCM VIDC BDC IBF[2:0] VIDO Reserved Description Stop Grant Time-out Counter Bus Divisor and VID Change Mode Voltage ID Control Bus Divisor - AMD AMD-K6-2/450 | Design Guide - Page 69
2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Embedded AMD Processor Recognition The CPUID instruction provides a simple way for hardware and software to identify the type of processor and its feature set. After detecting the processor and its capabilities, software - AMD AMD-K6-2/450 | Design Guide - Page 70
the AMD-K6E processor Model 7, all AMD processors support the CPUID instruction. However, it is still recommended that software verify that the CPUID instruction is supported. To use the CPUID instruction, software must first determine if the processor supports the CPUID instruction. CPUID support - AMD AMD-K6-2/450 | Design Guide - Page 71
AMD-K6™ Processors BIOS Design Guide If the value has changed, the CPUID instruction is available for identifying the processor and its features. The following code sample demonstrates the way a program uses the PUSHFD and POPFD instructions , no CPUID A potential problem with this approach is that - AMD AMD-K6-2/450 | Design Guide - Page 72
Processors (Model 8) X X X X X X X X - - AMD-K6™-2E+ and AMD-K6™-III AMD-K6™-IIIE+ Processor Processors (Model 9) (Model D) X X X X X X X X X X X X X X X X X X - X4 Identifying the Processor's Vendor Software must execute the standard function EAX=0. The CPUID instruction - AMD AMD-K6-2/450 | Design Guide - Page 73
Information Embedded AMD-K6™ Processors BIOS Design Guide AMD's definition for subsequent CPUID functions and the registers returned for those functions. Once the software identifies the processor's vendor, it knows the definition for all the functions supplied by the CPUID instruction. By using - AMD AMD-K6-2/450 | Design Guide - Page 74
by Function 1 Table 29. Processor Signatures for AMD-K6™ Processors Processor AMD-K6E Processor (Model 7) AMD-K6-2 Processor (Model 8) AMD-K6-2E Processor (Model 8) AMD-K6-III Processor (Model 9) AMD-K6-2E+ Processor (Model D) AMD-K6-IIIE+ Processor (Model D) Instruction Family 0101b (5h) 0101b - AMD AMD-K6-2/450 | Design Guide - Page 75
AMD-K6™ Processors BIOS Design Guide Identifying Supported supported using a 4-byte directory entry. 1 1 18-21 Reserved on all AMD processors 0 0 22 AMD Multimedia Instruction Extensions AMD additions to the original MMX™ instruction set are supported.3 0 1 Embedded AMD Processor - AMD AMD-K6-2/450 | Design Guide - Page 76
vendor specifiers combined with CPUID model numbers. The AMD-K6-2E+ and AMD-K6-IIIE+ processors add a new set of powerful extensions to the x86 instruction set - 3DNow! extensions. See the AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets Manual, order# 22466 for more information about these - AMD AMD-K6-2/450 | Design Guide - Page 77
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Detection Algorithm for Determining Instruction Set Support To simplify the detection of the new instructions and the original 3DNow! and MMX instructions, use the following algorithm. A code sample using - AMD AMD-K6-2/450 | Design Guide - Page 78
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 3DNow! Extensions Test AMD Multimedia Instruction Extensions Test 10. If bit 30 of the extended feature flags is set to 1, the additions to the 3DNow! instruction set are supported. 11. If bit 22 of the - AMD AMD-K6-2/450 | Design Guide - Page 79
!™ Technology Information Extended function 8000_0007h provides information regarding the processor's support for AMD PowerNow! and its enhanced power management (EPM) features. Based on the status of the EPM flags, software can determine if the processor supports programmable bus frequency control - AMD AMD-K6-2/450 | Design Guide - Page 80
Guide 23913A/0-November 2000 New AMD-K6™ Processor Instructions All models/steppings of the AMD-K6 processor family implement the following new instruction set: s MMX™ Instructions-57 new instructions for multimedia software. See the AMD-K6™ MMX™ Enhanced Processor Multimedia Technology Manual - AMD AMD-K6-2/450 | Design Guide - Page 81
Information Embedded AMD-K6™ Processors BIOS Design Guide Additional Considerations Software Timing Dependencies Relative to Memory Controller Setup Processors in the K86 family differ from other processors with regards to instruction latencies and the order or priority of processor bus cycles - AMD AMD-K6-2/450 | Design Guide - Page 82
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 sampling KEN# before it was valid (in this case, BRDY# was used by the processor to sample KEN#). If NA# is not asserted during memory write cycles, then the processor does not fully take advantage of the - AMD AMD-K6-2/450 | Design Guide - Page 83
Information Embedded AMD-K6™ Processors BIOS Design Guide Appendix A CPUID mnemonic opcode description CPUID 0F A2h Identify the processor and its feature set Privilege: none Registers Affected: EAX, EBX, ECX, EDX Flags Affected: none Exceptions Generated: none The CPUID instruction is - AMD AMD-K6-2/450 | Design Guide - Page 84
Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Standard Functions Function 0 - Largest Standard Function Input Value and Vendor Identification String Input: EAX = 0 Output: EAX = Largest function input value recognized by the CPUID instruction EBX, EDX - AMD AMD-K6-2/450 | Design Guide - Page 85
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide The standard feature flags are returned in the EDX register and indicate the presence of specific features. In most cases, a "1" indicates the feature is present, - AMD AMD-K6-2/450 | Design Guide - Page 86
all AMD processors 0 30 AMD 3DNow! Instruction Extensions 0 31 AMD 3DNow! Instructions 1 Notes: 1. Bit definitions: 0 = No Support, 1 = Support. AMD-K6-2 & AMD-K6-2E Processors (Model 8) 1 1 1 1 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 AMD-K6-III Processor (Model 9) AMD-K6-2E+ and AMD-K6 - AMD AMD-K6-2/450 | Design Guide - Page 87
November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Extended Functions Function 8000_0000h - Largest Extended Function Input Value Input: EAX = 8000_0000h Output: EAX = Largest function input value recognized by the CPUID instruction EBX = Reserved ECX = Reserved - AMD AMD-K6-2/450 | Design Guide - Page 88
AMD processors 30 AMD 3DNow! Instruction Extensions 31 3DNow! Instructions Notes: 1. Bit definitions: 0 = No Support, 1 = Support AMD-K6E Processor (Model 7) 1 1 1 1 1 1 0 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 AMD-K6-2 and AMD-K6-2E Processors (Model 8) 1 1 1 1 AMD-K6-2E+ and AMD-K6-III AMD-K6 - AMD AMD-K6-2/450 | Design Guide - Page 89
-K6™-III. The AMD CPUID utility v2.07 should be used to display the name string specified for AMD-K6E, Model D processors. This utility can be obtained from http: //www.amd.com/products/cpg/bin/amdcpuid.exe. Feature bits returned by the standard and extended function calls of the CPUID instruction - AMD AMD-K6-2/450 | Design Guide - Page 90
Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Function 8000_0005h - L1 Cache Information Input: EAX = 8000_0005h Output: EAX = Reserved EBX = TLB Information ECX = L1 Data Cache Information EDX = L1 Instruction Cache Information Function - AMD AMD-K6-2/450 | Design Guide - Page 91
on low-power versions of the AMD-K6-2E+ and AMD-K6-IIIE+ processors, Model D. Input: EAX = 8000_0007h Output: EAX = Reserved EBX = Reserved ECX = Reserved EDX = EPM Flags Function 8000_0007h returns information about the processor's AMD PowerNow! technology support. Table 37 provides the format - AMD AMD-K6-2/450 | Design Guide - Page 92
AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Cache Associativity Field Definitions This section describes the values returned in the associativity fields. Associativity for L1 Caches and L1 TLBs The associativity fields for the L1 data cache, L1 instruction cache, L1 data - AMD AMD-K6-2/450 | Design Guide - Page 93
AMD-K6™ Processors BIOS Design Guide Appendix B Values Returned by the CPUID Instruction Table 39 contains all the values returned for AMD-K6 processors by the CPUID instruction. Table 39. CPUID Values Returned by AMD-K6™ Processors 3320_296Dh2 7270_2044h2 AMD-K6-III Processor (Model 9) - AMD AMD-K6-2/450 | Design Guide - Page 94
AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Table 39. CPUID Values Returned by AMD-K6™ Processors (continued) Function Register Function: 8000_0003h AMD-K6E Processor (Model 7) AMD-K6-2 & AMD-K6-2E Processors (Model 8) AMD-K6-III Processor (Model 9) AMD-K6-2E+ & AMD-K6 - AMD AMD-K6-2/450 | Design Guide - Page 95
34 BF Signals 34 BIOS Considerations 6 BIOS boot strings 66 bus divisor control 56 cache invalidation 19 cache testing 7 CPU speed detection 6 CPUID instruction 6 displaying processor name 66 EFER recommended setting 26 model-specific registers (MSRs 6 shadowed 70 SMM issues 7 voltage - AMD AMD-K6-2/450 | Design Guide - Page 96
Bus Cycle Bit 54 Generation/Family 75 GSBC Bit 54 I I/O BASE Address Field 54 I/O Trap Dword configuration at offset FFA4h (table 13 differences in AMD-K6™ processors 13 IBF Field 56 ID Bit 58 INIT Signal 8-9 Inquire Cycles not supported during EPM stop grant state 55 Instructions 3DNow - AMD AMD-K6-2/450 | Design Guide - Page 97
Bit 36 Physical address generation 31 base address 31 Pin Bus Frequency Divisor Field 46 Pipelining support 69 write allocation methods 69 POPFD Instruction 59 POST Routine VIDC bit setting 56 Processor BIOS boot strings 6, 11, 66 bus frequency 34 determining signature 61 displaying name - AMD AMD-K6-2/450 | Design Guide - Page 98
Information Embedded AMD-K6™ Processors BIOS Design Guide Write Cycles out-of-order 25 Write Handling Control Register (WHCR) models 7 and 8‰[7:0 19 models 8‰[F:8], 9, and D 27 Write Merge Buffer 24-25 Write-Combining (WC) Memory 30-31 WRMSR Instruction 14, 16 L2 tag or data selection 42
-
1 -
2 -
3 -
4 -
5 -
6 -
7 -
8
-
9
-
10
-
11
-
12
-
13
-
14
-
15
-
16
-
17
-
18
-
19
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
29
-
30
-
31
-
32
-
33
-
34
-
35
-
36
-
37
-
38
-
39
-
40
-
41
-
42
-
43
-
44
-
45
-
46
-
47
-
48
-
49
-
50
-
51
-
52
-
53
-
54
-
55
-
56
-
57
-
58
-
59
-
60
-
61
-
62
-
63
-
64
-
65
-
66
-
67
-
68
-
69
-
70
-
71
-
72
-
73
-
74
-
75
-
76
-
77
-
78
-
79
-
80
-
81
-
82
-
83
-
84
-
85
-
86
-
87
-
88
-
89
-
90
-
91
-
92
-
93
-
94
-
95
-
96
-
97
-
98
 |
 |
®
Embedded
AMD-K6™
Processors
BIOS Design Guide
Publication #
23913
Rev:
A
Amendment/
0
Issue Date:
November 2000
Application Note