AMD AMD-K6-2/450 Design Guide - Page 17

23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide AMD-K6™-III Processor Model 9/[3:0] In addition to supporting the 3DNow! instruction set and a 100MHz processor bus, the AMD-K6-III processor contains a 256Kbyte backside L2 cache. Model 9/[3:0] is any of four possible model/steppings-models 9/0, 9/1, 9/2, or 9/3. Model 9/[3:0] is manufactured in the 0.25micron process. s Model 9/[3:0] implements the same ten MSRs as the Model 8/[F:8]. With the exception of bit 4 (L2D) in the EFER register, the bits and fields within these ten MSRs are defined identically. s Model 9/[3:0] supports one additional MSR for a total of eleven MSRs. AMD-K6™-IIIE+ Embedded Processor Model D/[3:0] In addition to supporting the 3DNow! instruction set and a 100MHz processor bus, the AMD-K6-IIIE+ processor contains a 256Kbyte backside L2 cache. It also supports the 3DNow! DSP instruction extensions. Low-power versions of the processor support AMD PowerNow! technology. Model D/[3:0] is any of four possible model/steppings-models D/0, D/1, D/2, or D/3. Model D/[3:0] is manufactured in the 0.18micron process. s Model D/[3:0] implements the same ten MSRs as the Model 8/[F:8]. With the exception of bit 4 (L2D) in the EFER register, the bits and fields within these ten MSRs are defined identically for standard-power versions. The PSOR register is defined differently for low-power versions. s Model D/[7:4] supports an additional MSR, the Level-2 Cache Array Access Register (L2AAR), for a total of eleven MSRs. s Low-power versions of Model D/[7:4] support an additional MSR, the Enhanced Power Management Register (EPMR), for a total of twelve MSRs. Processor Models and Steppings 5