AMD AMD-K6-2/450 Design Guide - Page 50

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Model 9 Registers The AMD-K6-III processor (Model 9) provides the eleven modelspecific registers listed in Table 19. The contents of ECX selects the MSR to be addressed by the RDMSR and WRMSR instruction. The AMD-K6-III processor contains a split Level-1 (L1) 64-Kbyte writeback cache organized as a separate 32-Kbyte instruction cache and a 32-Kbyte data cache with two-way set associativity. The cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. In addition, the processor also contains a 256-Kbyte, 4-way set associative, unified level-2 (L2) cache. Further performance gains are achieved by the implementation of a write allocation scheme. Table 19. Model-Specific Registers Supported by Model 9 Register Name Machine-Check Address Register Machine-Check Type Register Test Register 12 Time Stamp Counter Mnemonic MCAR MCTR TR12 TSC ECX Value 00h 01h 0Eh 10h Extended Feature Enable Register EFER C000_0080h Write Handling Control Register WHCR SYSCALL/SYSRET Target Address Register STAR UC/WC Cacheability Control Register UWCCR Processor State Observability Register PSOR C000_0082h C000_0081h C000_0085h C000_0087h Page Flush/Invalidate Register PFIR C000_0088h Level-2 Cache Array Access Register L2AAR C000_0089h Description page 16 page 16 page 16 page 16 page 39 page 27 Comments Identical on all models Identical on all models Identical on all models Identical on all models Adds L2 Disable bit (L2D) to Model 8/[F:8] implementation Identical to Model 8/[F:8] page 22 Identical to Model 8/[7:0] page 30 page 34 page 36 page 40 Identical to Model 8/[F:8] Identical to Model 8/[F:8] Identical to Model 8/[F:8]. The invalidate and flush operations affect both the L1 and L2 caches on the AMD-K6-III processor. New for Model 9 38 Model 9 Registers