AMD AMD-K6-2/450 Design Guide - Page 30
Extended Feature Enable Register (EFER), - faults
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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Extended Feature Enable Register (EFER) The Extended Feature Enable Register (EFER) contains the control bits that enable the extended features of the AMD-K6 processor. Figure 2 shows the format of the EFER register, and Table 10 defines the function of each bit of the EFER register. The EFER register is MSR C000_0080h. 63 10 S C E Reserved Symbol Description Bit SCE System Call Extension 0 Figure 2. Extended Feature Enable Register (EFER) (Models 7 and 8/[7:0]) Table 10. Extended Feature Enable Register (EFER) Definition (Models 7 and 8/[7:0]) Bit Description 63-1 Reserved 0 System Call Extension (SCE)1 R/W Function R Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. R/W SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions. Notes: 1. The AMD-K6E processor Model 7 provides the SCE bit in the EFER register, but this bit does not affect processor operation because the SYSCALL and SYSRET instructions and the STAR register are not supported in this models. 18 Model 7 and Model 8/[7:0] Registers