AMD AMD-K6-2/450 Design Guide - Page 59
NOL2 Bit, STEP Field, EBF[2:0] Field, Stamp Counter method See Time Stamp Counter TSC
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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide NOL2 Bit STEP Field EBF[2:0] Field This read-only bit indicates whether the processor contains an L2 cache. Note: This bit is always set to 0 for Model D. This read-only field contains the stepping ID. This is identical to the value returned by CPUID standard function 1 in EAX[3:0]. This read-only field contains the effective value of the BF divisor supplied to the processor's internal PLL, which allows the BIOS to determine the frequency of the host bus. s The core frequency must first be determined using the Time Stamp Counter method (See "Time Stamp Counter (TSC)" on page 16). s The core frequency is then divided by the processor-to-bus clock ratio as determined by the EBF field of the PSOR register (see Table 23). s The result is the frequency of the processor bus. Table 23. Processor-to-Bus Clock Ratios (Low-Power Model D) State of EBF[2:0] 100b 101b 110b 111b 000b 001b 010b 011b Processor-to-Bus Clock Ratio 2.0x1 3.0x 6.0x 3.5x 4.5x 5.0x 4.0x 5.5x Notes: 1. The 2.5x ratio that was supported on Models 8 and 9 is not supported on low-power Model D. Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b. Model D Registers 47