AMD AMD-K6-2/450 Design Guide - Page 68

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 31 12 11 10 9 8 7 54 0 BV SGTC V C I D BDC IBF[2:0] VIDO MC Symbol SGTC BVCM VIDC BDC IBF[2:0] VIDO Reserved Description Stop Grant Time-out Counter Bus Divisor and VID Change Mode Voltage ID Control Bus Divisor Control Internal BF Divisor Voltage ID Output Bits 31-12 11 10 9-8 7-5 4-0 Figure 28. Bus Divisor and Voltage ID Control (BVC) Field (Low-Power Model D) Table 27. Bus Divisor and Voltage ID Control (BVC) Definition (Low-Power Model D) Bit Description 31-12 Stop Grant Time-out Counter (SGTC) 11 Bus Divisor and VID Change Mode (BVCM) 10 Voltage ID Control (VIDC) 9-8 Bus Divisor Control (BDC) 7-5 Internal BF Divisor (IBF) 4-0 Voltage ID Output (VIDO) R/W Function1 Writing a non-zero value to this field causes the processor to enter the W EPM Stop Grant state internally. This 20-bit value is multiplied by 4096 to determines the duration of the EPM Stop Grant state, measured in processor bus clocks. This bit controls the mode in which the bus-divisor and the voltage con- R/W trol bits are allowed to change. If BVCM=0, the Bus Divisor and Voltage ID changes take effect only upon entering the EPM Stop Grant state as a result of the SGTC field being programmed. BVCM=1 is reserved. This bit controls the mode of Voltage ID control. If VIDC=0, the processor VID[4:0] pins are unchanged upon entering the EPM Stop Grant R/W state. If VIDC=1, the processor VID[4:0] pins are programmed to the VIDO value upon entering the EPM Stop Grant state. BIOS should initialize this bit to 1 during the POST routine. This 2-bit field controls the mode of bus divisor control. If BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling edge of R/W RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled upon entering the EPM Stop Grant state. BDC[1:0]=01b is reserved. BIOS should initialize these bits to 10b during the POST routine. R/W If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is programmed to the IBF[2:0] value upon entering the EPM Stop Grant state. This 5-bit value is driven out on the processor VID[4:0] pins upon enterR/W ing the EPM Stop Grant state if the VIDC bit=1. These bits are initialized to 01010b and driven on the processor VID[4:0] pins at RESET. Notes: 1. All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b. 56 Model D Registers