AMD AMD-K6-2/450 Design Guide - Page 27
AMD-K6™ Family continued, Table 8., Summary by Model of MSR Differences within the AMD-K6™ Family
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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Table 7. Summary by Register of MSR Differences within the AMD-K6™ Family (continued) Register Level-2 Cache Array Access Register Enhanced Power Management Register Notes: 1. Standard-power versions only. 2. Low-power versions only. Mnemonic ECX Value Models 7, 8 L2AAR C000_0089h 9 D EPMR 7, 8, 9, D1 C000_0086h D2 Description Not supported page 40 page 48 Not supported page 54 Table 8. Summary by Model of MSR Differences within the AMD-K6™ Family EFER2 WHCR3 PSOR Standard L2D EWBEC DPE SCE Model Stepping MSRs1 508 MB 4092 MB STAR UWCCR PBF BF VID EBF PFIR L2AAR EPMR 7 All X XX 8 7:0 X XX X 8 F:8 X X XX XX XX X 9 3:0 X X X XX XX XX X X 3:0 D 7:4 X X X XX XX X X4 X5 X X X5 Notes: 1. There are four MSRs that every model and stepping of the AMD-K6 family of processors support identically-MCAR, MCTR, TR12, and TSC. 2. L2D, EWBEC, and DPE are bits/fields supported in EFER for the indicated models/steppings. All models/steppings support the System Call Extension (SCE) bit in EFER, even if the corresponding SYSCALL and SYSRET instructions and the STAR register are not supported. 3. Indicates whether the WAELIM field supports 508 Mbytes or 4092 Mbytes of memory. The location of the WAE15M bit and the WAELIM field within the WHCR register differs between the models/steppings that support 508 Mbytes of memory and those that support 4092 Mbytes of memory. 4. Supported on standard-power versions only. 5. Supported on low-power versions only. Model-Specific Registers Overview 15