AMD AMD-K6-2/450 Design Guide - Page 95

23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Index A Address Generation 31 AMD PowerNow!™ Technology determining information 67 enabling EPM features 54 enhanced power management register (EPMR 54 EPM 16-byte I/O block 55 EPM stop grant clock control state 55 AMD Processor Signature 75 AMD-K6™ Processor Family features (table 2 model-specific register (MSR) differences (table) . . 14-15 AMD-K6™-2 Processor 3 model-specific registers supported (table 17, 23 AMD-K6™-2E Embedded Processor 4 model-specific registers supported (table 23 AMD-K6™-2E+ Embedded Processor 4 model-specific registers supported (table 45 AMD-K6™E Embedded Processor 3 model-specific registers supported (table 17 AMD-K6™-III Processor 5 model-specific registers supported (table 38 AMD-K6™-IIIE+ Embedded Processor 5 model-specific registers supported (table 45 Associativity field definitions 80 L1 caches and L1 TLBs 80 L2 cache 80 L2 cache values (table 80 AuthenticAMD 60, 65, 72 B BDC Field 56 BF Field 34 BF Signals 34 BIOS Considerations 6 BIOS boot strings 66 bus divisor control 56 cache invalidation 19 cache testing 7 CPU speed detection 6 CPUID instruction 6 displaying processor name 66 EFER recommended setting 26 model-specific registers (MSRs 6 shadowed 70 SMM issues 7 voltage ID control 56 write allocate limit 20 write allocate mechanisms 69 BIST 10 BRDY# Signal 69 Built-In Self-Test (BIST 13 Bus Divisor and VID Change Mode Bit 56 Bus Divisor and Voltage ID Control Bit 55 Bus Divisor Control Field 56 Bus Frequency 34 BVC Field 55 BVCM Bit 56 C Cache associativity 80 associativity values for L2 cache (table 80 displaying information 67 L2 tag writing 43, 53 testing 7 Cache Inhibit Bit 16 CD Bit 9 CI Bit 16 CLI Instruction 59 CMOV Instruction 63 CMPXCHG8B Instruction 63 CPUID Instruction 2, 6, 65, 71 EFLAGS ID-bit test 58 flow chart (figure 12 functions 59 functions in embedded AMD processors (table 60 identification algorithms 11 illegal instruction exception test 58 overview 57 sample code 67 test 65 testing 58 values returned (table 81 CR0 Register 9 CR4 Register 16 E EAS Register time stamp counter value 16 EAX Register BIST 10 extended function 8000_0001h (figure 66 function 1 (figure 62 L2 tag information 43, 52 EBF Field 47 EBX Register function 8000_0005h (table 78 ECX Register 16 function 8000_0005h (table 78 function 8000_0006h (table 79 MSR selection 17 EDX Register cache access 40 extended feature flags 75 function 8000_0005h (table 78 function 8000_0007h (table 79 ignored fields during L2 tag access 42 L2 tag or data location 41, 50 standard feature flags 73 time stamp counter value 16 Effective Bus Frequency Divisor Field 47 EFLAGS Register 58 EIP Address 22 EN Bit 54 Enable AMD PowerNow! Technology Management Bit . . . . 54 Enhanced Power Management 79 determining information 67 enabling EPM features 54 Enhanced Power Management Register (EPMR 54 EPM 16-Byte I/O Block 55 EPM Stop Grant Clock Control State 55 EWBE# Signal 24-26 Extended Feature Enable Register (EFER) EWBEC settings (table 26 model 8‰[F:8 24 models 7 and 8‰[7:0 18 models 9 and D 39 Extended Features flag descriptions (table 76 standard and extended feature bits (table 63 Extended Functions 75 testing 61 83