AMD AMD-K6-2/450 Design Guide - Page 52

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Level-2 Cache Array Access Register (L2AAR) Models 9 and D provide the L2AAR register that allows for direct access to the L2 cache and L2 tag arrays. The L2 cache in the AMD-K6-III processor is organized as shown in Figure 11: s Four 64-Kbyte ways s Each way contains 1024 sets s Each set contains four 64-byte sectors (one sector in each way) s Each sector contains two 32-byte cache lines s Each cache line contains four 8-byte octets s Each octet contains an upper and lower dword (4 bytes) Each line within a sector contains its own MESI state bits, and associated with each sector is a tag and least recently used (LRU) information. Set 0 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU Way 0 Way 1 Way 2 Way 3 1024 sets Set 1023 Figure 11. L2 Cache Organization (AMD-K6™-III Processor) The L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed-RDMSR or WRMSR-and the contents of the EDX register. The EDX register specifies the location of the access, and whether the access is to the L2 cache data or tags (see Figure 13 on page 41). Figure 12 on page 41 shows the L2 cache sector and line organization. If bit 5 (see Figure 13) of the address of a cache line equals 1, then this cache line is stored in Line 1 of a sector. Similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in Line 0 of a sector. 40 Model 9 Registers