AMD AMD-K6-2/450 Design Guide - Page 65

Writing to L2 Tag of AMDK6IIIE+ Processor, which the tag is being written-that is

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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 7 654 Way 0 Way 1 3 21 0 Way 2 Way 3 Writing to L2 Tag of AMD-K6-IIIE+ Processor LRU Values 00b Most Recently Used 01b Used More Recently Than 10b, But Less Recently Than 00b 10b Used More Recently Than 11b, But Less Recently Than 01b 11b Least Recently Used Figure 25. LRU Byte (same as Figure 16) When writing to the L2 tag of the AMD-K6-IIIE+ processor, special consideration must be given to the least significant bit of the Tag field of the EAX register- EAX[15]. The length of the L2 tag required to support the 256-Kbyte L2 cache on the AMD-K6-III and AMD-K6-IIIE+ is 16 bits, which corresponds to bits 31:16 of the EAX register. However, the AMD-K6-IIIE+ processor provides a total of 17 bits for storing the L2 tag-that is, 16 bits for the tag (EAX[31:16]), plus an additional bit for internal purposes (EAX[15]). During normal operation, the AMD-K6-III and AMD-K6-IIIE+ ensure that this additional bit (bit 15) always corresponds to the set in which the tag resides. Note that bits 15:6 of the address determine the set, in which case bit 15 equal to 0 addresses sets 0 through 511, and bit 15 equal to 1 addresses sets 512 through 1023. In order to set the full 17-bit L2 tag properly when using the L2AAR register, EAX[15] must likewise correspond to the set in which the tag is being written-that is, EAX[15] must be equal to EDX[15] (refer to Figure 21 on page 50 and Figure 24 on page 52). It is important to note that this special consideration is only required if the AMD-K6-IIIE+ processor will subsequently be expected to properly execute instructions or access data from the L2 cache following the setup of the L2 cache by means of the L2AAR register. If the intent of using the L2AAR register is solely to test or debug the L2 cache without the subsequent intent of executing instructions or accessing data from the L2 cache, then this consideration is not required. Note: This special consideration when writing to the L2 tag is not applicable to the AMD-K6-2E+ processor. Model D Registers 53

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Model D Registers
53
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Figure 25.
LRU Byte (same as Figure 16)
Writing to L2 Tag of
AMD-K6-
III
E+
Processor
When writing to the L2 tag of the AMD-K6-IIIE+ processor,
special consideration must be given to the least significant bit
of the Tag field of the EAX register— EAX[15]. The length of
the L2 tag required to support the 256-Kbyte L2 cache on the
AMD-K6-III and AMD-K6-IIIE+ is 16 bits, which corresponds to
bits 31:16 of the EAX register. However, the AMD-K6-IIIE+
processor provides a total of 17 bits for storing the L2 tag—that
is, 16 bits for the tag (EAX[31:16]), plus an additional bit for
internal purposes (EAX[15]). During normal operation, the
AMD-K6-III and AMD-K6-IIIE+ ensure that this additional bit
(bit 15) always corresponds to the set in which the tag resides.
Note that bits 15:6 of the address determine the set, in which
case bit 15 equal to 0 addresses sets 0 through 511, and bit 15
equal to 1 addresses sets 512 through 1023.
In order to set the full 17-bit L2 tag properly when using the
L2AAR register, EAX[15] must likewise correspond to the set in
which the tag is being written—that is, EAX[15] must be equal
to EDX[15] (refer to Figure 21 on page 50 and Figure 24 on
page 52).
It is important to note that this special consideration is only
required if the AMD-K6-IIIE+ processor will subsequently be
expected to properly execute instructions or access data from
the L2 cache following the setup of the L2 cache by means of
the L2AAR register. If the intent of using the L2AAR register is
solely to test or debug the L2 cache without the subsequent
intent of executing instructions or accessing data from the L2
cache, then this consideration is not required.
Note:
This special consideration when writing to the L2 tag is not
applicable to the AMD-K6-2E+ processor.
7
6
5
4
3
2
1
0
Way 2
LRU Values
00b Most Recently Used
01b Used More Recently Than 10b, But Less Recently Than 00b
10b Used More Recently Than 11b, But Less Recently Than 01b
11b Least Recently Used
Way 3
Way 0
Way 1