AMD AMD-K6-2/450 Design Guide - Page 21
Processor State after INIT, AMD-K6™-2E+ Model D, AMD-K6™, Model 9,
View all AMD AMD-K6-2/450 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 21 highlights
23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Table 4. AMD-K6™-2E+ (Model D), AMD-K6™-III (Model 9), and AMD-K6™-IIIE+ Processors (Model D) State after RESET Register EDX EFER2 L2AAR PFIR PSOR STAR UWCCR WHCR EPMR4 RESET State 0000_05MSh1 0000_0000_0000_0002h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_00SBh1,3 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h 0000_0000_0000_0000h Notes: 1. "M" represents the Model and "S" represents the Stepping. 2. Because EFER[4] equals 0 after RESET, the L2 cache is enabled by default after RESET. 3. "B" represents PSOR[3:0], where PSOR[3] equals 0, and PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of RESET. 4. Supported on low-power versions only of Model D processors. Processor State after INIT The assertion of INIT causes the processor to empty its pipelines, initialize most of its internal state, and branch to address FFFF_FFF0h-the same instruction execution starting point used after RESET. Unlike RESET, the processor preserves the contents of its caches, the floating-point state, the SMM base, MSRs, and the CD and NW bits of the CR0 register. The edge-sensitive interrupts FLUSH# and SMI# are sampled and preserved during the INIT process and are handled accordingly after the initialization is complete. However, the processor resets any pending NMI interrupt upon sampling INIT asserted. INIT can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. States after RESET and INIT 9