AMD AMD-K6-2/450 Design Guide - Page 22
BuiltIn SelfTest (BIST), L1 instruction and data caches
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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Built-In Self-Test (BIST) Fo r a l l m o d e l s o f t h e A M D -K 6 p ro c e ss o r, B I S T i s run unconditionally following the falling transition of RESET. The results of the test are contained in the general-purpose register EAX. If EAX contains 0000_0000h, then BIST was successful. If the contents of EAX are non-zero, the BIST failed. The internal resources tested during BIST include the following: s L1 instruction and data caches s L2 unified cache (models 9 and D only) s Instruction and data translation lookaside buffers (TLBs) 10 States after RESET and INIT
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10
States after RESET and INIT
Embedded AMD-K6™ Processors BIOS Design Guide
23913A/0—November 2000
Preliminary Information
Built-In Self-Test (BIST)
For all models of the AMD-K6 processor, BIST is run
unconditionally following the falling transition of RESET. The
results of the test are contained in the general-purpose register
EAX. If EAX contains 0000_0000h, then BIST was successful. If
the contents of EAX are non-zero, the BIST failed. The internal
resources tested during BIST include the following:
■
L1 instruction and data caches
■
L2 unified cache (models 9 and D only)
■
Instruction and data translation lookaside buffers (TLBs)