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Using CPUID Functions, When software uses the CPUID instruction to identify

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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide If the value has changed, the CPUID instruction is available for identifying the processor and its features. The following code sample demonstrates the way a program uses the PUSHFD and POPFD instructions to test the ID bit. pushfd pop eax mov ebx, eax xor eax, 00200000h push eax popfd pushfd pop eax cmp eax, ebx jz NO_CPUID ; Save EFLAGS to stack ; Store EFLAGS in EAX ; Save in EBX for testing later ; Switch bit 21 ; Copy changed value to stack ; Save changed EAX to EFLAGS ; Push EFLAGS to top of stack ; Store EFLAGS in EAX ; See if bit 21 has changed ; If no change, no CPUID A potential problem with this approach is that an interrupt or a trap (such as a debug trap) can occur between the POPFD and the following PUSHFD, and that the interrupt or trap handler code destroys the value of the ID bit. Where possible, the above code should be preceded by a CLI instruction and followed by an STI instruction, which ensures that no interrupts occur between the POPFD and the PUSHFD. However, traps can still occur, even if the code is preceded by a CLI instruction and followed by an STI instruction. Using CPUID Functions When software uses the CPUID instruction to identify a process or, it is impo rt ant t hat it uses t he inst ruc tio n appropriately. The instruction has been defined to make it easy to identify the type and features of x86 processors manufactured by many different vendors. The standard functions (EAX=0 and EAX=1) are the same for all processors. Having standard functions simplifies software's task of testing for and implementing features common to x86 processors. Software can test for these features and, as new x86 processors are released, benefit from these capabilities immediately. Extended functions are specific to a vendor's processor. These functions provide additional information about AMD processors that software can use to identify enhanced features and functions. To test for extended functions, software checks Embedded AMD Processor Recognition 59

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
Introduction	13
Audience	13
Processor Models and Steppings	14
AMDK6™E Embedded Processor	15
Model 7	15
AMDK6™2 Processor	15
Model 8/[7:0]	15
Model 8/[F:8]	15
AMDK6™2E Embedded Processor	16
Model 8/[F:8]	16
AMDK6™2E+ Embedded Processor	16
Model D/[7:4]	16
AMDK6™III Processor	17
Model 9/[3:0]	17
AMDK6™IIIE+ Embedded Processor	17
Model D/[3:0]	17
BIOS Consideration Checklist	18
CPUID	18
CPU Speed Detection	18
ModelSpecific Registers (MSRs)	18
Cache Testing	19
SMM Issues	19
States after RESET and INIT	20
Register States after RESET and INIT	20
Processor State after INIT	21
BuiltIn SelfTest (BIST)	22
CPUID Identification Algorithms	23
System Management Mode (SMM)	25
StateSave Map Differences	25
I/O Trap Dword Differences	25
ModelSpecific Registers Overview	26
Standard Model-Specific Registers (All Models)	28
MachineCheck Address Register (MCAR) and MachineCheck Type Register (MCTR)	28
Test Register 12 (TR12)	28
Time Stamp Counter (TSC)	28
Model 7 and Model 8/[7:0] Registers	29
Extended Feature Enable Register (EFER)	30
Write Handling Control Register (WHCR)	31
Write Allocation	31
Write Cacheability Detection Enable Bit	32
Write Allocate Enable Limit Field	32
Write Allocate Enable 15to16Mbyte Field.	33
SYSCALL/SYSRET Target Address Register (STAR)	34
Model 8/[F:8] Registers	35
Extended Feature Enable Register (EFER)	36
External Write Buffer Empty Control Field	36
Write Handling Control Register (WHCR)	39
Write Allocation	39
Write Allocate Enable Limit Field	40
Write Allocate Enable 15to16Mbyte Field	41
UC/WC Cacheability Control Register (UWCCR)	42
Physical Base Address n (n=0, 1)	43
Physical Address Mask n (n=0, 1)	43
WCn (n=0, 1)	43
UCn (n=0, 1)	43
Memory-Range Restrictions	44
Examples	45
Processor State Observability Register (PSOR)	46
NOL2 Bit	46
STEP Field	46
BF Field	46
Page Flush/Invalidate Register (PFIR)	48
LINPAGE Field	48
PF Bit	48
F/I Bit	49
Model 9 Registers	50
Extended Feature Enable Register (EFER)	51
Level-2 Cache Array Access Register (L2AAR)	52
LRU (Least Recently Used) Field	55
Writing to L2 Tag of AMDK6™III Processor	55
Model D Registers	57
Processor State Observability Register (PSOR) (Low-Power Versions)	58
PBF[2:0] Field	58
VID Field	58
NOL2 Bit	59
STEP Field	59
EBF[2:0] Field	59
Level-2 Cache Array Access Register (L2AAR)	60
LRU (Least Recently Used) Field	64
Writing to L2 Tag of AMDK6IIIE+ Processor	65
Enhanced Power Management Register (EPMR) (Low-Power Versions)	66
EPM 16-Byte I/O Block (Low-Power Versions Only)	67
BVC Field	67
Embedded AMD Processor Recognition	69
CPUID Instruction Overview	69
Testing for the CPUID Instruction	70
Illegal Instruction Exception Method	70
EFLAGS IDBit Method	70
Using CPUID Functions	71
Identifying the Processor’s Vendor	72
Testing For Extended Functions	73
Determining the Processor Signature	73
Identifying Supported Features	75
Determining Instruction Set Support	76
Detection Algorithm for Determining Instruction Set Support	77
CPUID Test	77
Standard Function Test	77
MMX™ Test	77
Optional SSE Test	77
Extended Functions Test	77
3DNow!™ Test	77
Vendor Check	77
3DNow! Extensions Test	78
AMD Multimedia Instruction Extensions Test	78
AMD Processor Signature (Extended Function)	78
Displaying the Processor’s Name	78
Displaying Cache Information	79
Determining AMDPowerNow!™ Technology Information	79
Sample Code	79
New AMDK6™ Processor Instructions	80
Additional Considerations	81
Software Timing Dependencies Relative to Memory Controller Setup	81
Pipelining Support	81
Read-Only Memory	82
Appendix A	83
CPUID	83
Standard Functions	84
Extended Functions	87
Cache Associativity Field Definitions	92
Associativity for L1 Caches and L1 TLBs	92
Associativity for L2 Cache	92
Appendix B	93
Values Returned by the CPUID Instruction	93

Match case Limit results 1 per page

Embedded AMD Processor Recognition

23913A/0—November 2000

Embedded AMD-K6™ Processors BIOS Design Guide

Preliminary Information

If the value has changed, the CPUID instruction is available for

identifying the processor and its features. The following code

sample demonstrates the way a program uses the PUSHFD and

POPFD instructions to test the ID bit.

pushfd

; Save EFLAGS to stack

pop

eax

; Store EFLAGS in EAX

mov

ebx, eax

; Save in EBX for testing later

xor

eax, 00200000h

; Switch bit 21

push

eax

; Copy changed value to stack

popfd

; Save changed EAX to EFLAGS

pushfd

; Push EFLAGS to top of stack

pop

eax

; Store EFLAGS in EAX

cmp

eax, ebx

; See if bit 21 has changed

NO_CPUID

; If no change, no CPUID

A potential problem with this approach is that an interrupt or a

trap (such as a debug trap) can occur between the POPFD and

the following PUSHFD, and that the interrupt or trap handler

code destroys the value of the ID bit. Where possible, the above

code should be preceded by a CLI instruction and followed by

an STI instruction, which ensures that no interrupts occur

between the POPFD and the PUSHFD. However, traps can still

occur, even if the code is preceded by a CLI instruction and

followed by an STI instruction.

Using CPUID Functions

When software uses the CPUID instruction to identify a

processor, it is important that it uses the instruction

appropriately. The instruction has been defined to make it easy

to identify the type and features of x86 processors

manufactured by many different vendors.

The standard functions (EAX=0 and EAX=1) are the same for

all processors. Having standard functions simplifies software’s

task of testing for and implementing features common to x86

processors. Software can test for these features and, as new x86

processors are released, benefit from these capabilities

immediately.

Extended functions are specific to a vendor’s processor. These

functions provide additional information about AMD

processors that software can use to identify enhanced features

and functions. To test for extended functions, software checks