AMD AMD-K6-2/450 Design Guide - Page 97

23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide P Page Flush 36 Page Flush/Invalidate Register (PFIR) models 8‰[F:8], 9, and D 36 PBF Field 46 Performance EWBEC field settings (table 26 L2 cache disable setting 39 merging multiple write cycles 30 tuning 11, 57 write allocation 19 write ordering 25-26 PF Bit 36 Physical address generation 31 base address 31 Pin Bus Frequency Divisor Field 46 Pipelining support 69 write allocation methods 69 POPFD Instruction 59 POST Routine VIDC bit setting 56 Processor BIOS boot strings 6, 11, 66 bus frequency 34 determining signature 61 displaying name 6, 11, 66 extended functions 75 identifying supported features 63 identifying vendor 60 models 2 name string 77 recognition 57 signature (extended function 66, 75 signature (standard function 72 signatures for embedded AMD processors (table) . . . . . 62 speed detection 6 standard functions 72 state after INIT 9 state after RESET (table 8-9 steppings 2 Processor State Observability Register (PSOR) model D low-power 46 models 8‰[F:8], 9, and standard-power D 34 Processor-to-Bus Clock Ratios model D low-power (table 47 model D standard-power (table 35 models 8‰[F:8]) and 9 (table 35 PUSHFD Instruction 58 R RDMSR Instruction 14, 16 L2 tag or data selection 42 RDTSC Instruction 16 Read-Only Memory 70 Real-Time Clock (RTC 6 Refresh 69 Registers enhanced power management (EPMR 54 extended feature enable (EFER 18, 24, 39 level-2 cache array access (L2AAR 40, 48 machine-check address (MCAR 16 machine-check type (MCTR 16 page flush/invalidate (PFIR 36 processor state observability (PSOR 34, 40, 46 states after RESET and INIT 8 SYSCALL/SYSRET target address (STAR 22 test 12 16 time stamp counter (TSC 16 UC/WC cacheability control (UWCCR 30 write handling control (WHCR 19, 27 RESET Signal 8, 34 RESET State model 8/[F:8 8 models 7 and 8‰[7:0 8 models 9 and D 9 S SGTC Field 56 SMI# Signal 9, 13 Snoop Cycles not supported during EPM stop grant state 55 Software memory controller setup 69 timing dependencies 69 Special Bus Cycles 54 Speed Detection 6 Standard Features flag descriptions (table 74 standard and extended feature bits (table 63 Standard Functions 72 State-Save Map Differences 13 STEP Field 34 Stepping 34 Stepping ID 72, 75 STI Instruction 59 Stop Grant Time-out Counter Field 56 Streaming SIMD Extensions (SSE 65 SYSCALL Instruction 18, 22 SYSCALL/SYSRET Target Address Register (STAR) models 8‰[F:8], 9, and D 22 SYSENTER Instruction 61 SYSEXIT Instruction 61 SYSRET Instruction 18, 22 System Management Mode (SMM 13 I/O trap dword differences 13 issues 7 state-save map differences 13 T Test Register 12 (TR12 16 Time Stamp Counter (TSC 16 TLB 78 U UC/WC Cacheability Control Register (UWCCR) model 8‰[F:8], 9, and D 30 valid masks and range sizes (table 32 Uncacheable (UC) Memory 30 V Vendor Identification String 72 VID Field 46 VID[4:0] Outputs 46 VIDC Bit 56 VIDO Field 56 Voltage ID Control Bit 56 Voltage ID Output Field 56 W WAE15M Bit 21 WAELIM Field 20, 69 WBINVD Instruction 19 WC/UC Memory Type for UWCCR Register (table 31 WCDE Bit 69 Write Allocation methods 20 WAELIM 69 WCDE 69 85