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AMD AMD-K6-2/450 Design Guide - Page 61

AMD-K6-IIIE+ processor 1024 sets. Bit 20 of EDX T/D,

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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide The L2AAR register is MSR C000_0089h. The operation that is performed on the L2 cache is a function of the instruction executed-RDMSR or WRMSR-and the contents of the EDX register. The EDX register specifies the location of the access, and whether the access is to the L2 cache data or tags (refer to Figure 20 on page 50 for the AMD-K6-2E+ processor and Figure 21 on page 50 for the AMD-K6-IIIE+ processor). Figure 19 shows the L2 cache sector and line organization. If bit 5 (refer to Figure 20 for the AMD-K6-2E+ processor and Figure 21 for the AMD-K6-IIIE+ processor) of the address of a cache line equals 1, then this cache line is stored in Line 1 of a sector. Similarly, if bit 5 of the address of a cache line equals 0, then this cache line is stored in Line 0 of a sector. Octet 0 Octet 1 Octet 2 Octet 3 Upper Dword Lower Dword Upper Dword Lower Dword Line 1 Line 0 Sector Figure 19. L2 Cache Sector and Line Organization (same as Figure 12) Bit 15 of EDX, which is the most significant bit of the Set field, is not used for the AMD-K6-2E+ because there are half as many sets implemented on the AMD-K6-2E+ (512 sets) as the AMD-K6-IIIE+ processor (1024 sets). Bit 20 of EDX (T/D) determines whether the access is to the L2 cache data or tag. Table 24 on page 51 describes the operation that is performed based on the instruction and the T/D bit. Model D Registers 49

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
Introduction	13
Audience	13
Processor Models and Steppings	14
AMDK6™E Embedded Processor	15
Model 7	15
AMDK6™2 Processor	15
Model 8/[7:0]	15
Model 8/[F:8]	15
AMDK6™2E Embedded Processor	16
Model 8/[F:8]	16
AMDK6™2E+ Embedded Processor	16
Model D/[7:4]	16
AMDK6™III Processor	17
Model 9/[3:0]	17
AMDK6™IIIE+ Embedded Processor	17
Model D/[3:0]	17
BIOS Consideration Checklist	18
CPUID	18
CPU Speed Detection	18
ModelSpecific Registers (MSRs)	18
Cache Testing	19
SMM Issues	19
States after RESET and INIT	20
Register States after RESET and INIT	20
Processor State after INIT	21
BuiltIn SelfTest (BIST)	22
CPUID Identification Algorithms	23
System Management Mode (SMM)	25
StateSave Map Differences	25
I/O Trap Dword Differences	25
ModelSpecific Registers Overview	26
Standard Model-Specific Registers (All Models)	28
MachineCheck Address Register (MCAR) and MachineCheck Type Register (MCTR)	28
Test Register 12 (TR12)	28
Time Stamp Counter (TSC)	28
Model 7 and Model 8/[7:0] Registers	29
Extended Feature Enable Register (EFER)	30
Write Handling Control Register (WHCR)	31
Write Allocation	31
Write Cacheability Detection Enable Bit	32
Write Allocate Enable Limit Field	32
Write Allocate Enable 15to16Mbyte Field.	33
SYSCALL/SYSRET Target Address Register (STAR)	34
Model 8/[F:8] Registers	35
Extended Feature Enable Register (EFER)	36
External Write Buffer Empty Control Field	36
Write Handling Control Register (WHCR)	39
Write Allocation	39
Write Allocate Enable Limit Field	40
Write Allocate Enable 15to16Mbyte Field	41
UC/WC Cacheability Control Register (UWCCR)	42
Physical Base Address n (n=0, 1)	43
Physical Address Mask n (n=0, 1)	43
WCn (n=0, 1)	43
UCn (n=0, 1)	43
Memory-Range Restrictions	44
Examples	45
Processor State Observability Register (PSOR)	46
NOL2 Bit	46
STEP Field	46
BF Field	46
Page Flush/Invalidate Register (PFIR)	48
LINPAGE Field	48
PF Bit	48
F/I Bit	49
Model 9 Registers	50
Extended Feature Enable Register (EFER)	51
Level-2 Cache Array Access Register (L2AAR)	52
LRU (Least Recently Used) Field	55
Writing to L2 Tag of AMDK6™III Processor	55
Model D Registers	57
Processor State Observability Register (PSOR) (Low-Power Versions)	58
PBF[2:0] Field	58
VID Field	58
NOL2 Bit	59
STEP Field	59
EBF[2:0] Field	59
Level-2 Cache Array Access Register (L2AAR)	60
LRU (Least Recently Used) Field	64
Writing to L2 Tag of AMDK6IIIE+ Processor	65
Enhanced Power Management Register (EPMR) (Low-Power Versions)	66
EPM 16-Byte I/O Block (Low-Power Versions Only)	67
BVC Field	67
Embedded AMD Processor Recognition	69
CPUID Instruction Overview	69
Testing for the CPUID Instruction	70
Illegal Instruction Exception Method	70
EFLAGS IDBit Method	70
Using CPUID Functions	71
Identifying the Processor’s Vendor	72
Testing For Extended Functions	73
Determining the Processor Signature	73
Identifying Supported Features	75
Determining Instruction Set Support	76
Detection Algorithm for Determining Instruction Set Support	77
CPUID Test	77
Standard Function Test	77
MMX™ Test	77
Optional SSE Test	77
Extended Functions Test	77
3DNow!™ Test	77
Vendor Check	77
3DNow! Extensions Test	78
AMD Multimedia Instruction Extensions Test	78
AMD Processor Signature (Extended Function)	78
Displaying the Processor’s Name	78
Displaying Cache Information	79
Determining AMDPowerNow!™ Technology Information	79
Sample Code	79
New AMDK6™ Processor Instructions	80
Additional Considerations	81
Software Timing Dependencies Relative to Memory Controller Setup	81
Pipelining Support	81
Read-Only Memory	82
Appendix A	83
CPUID	83
Standard Functions	84
Extended Functions	87
Cache Associativity Field Definitions	92
Associativity for L1 Caches and L1 TLBs	92
Associativity for L2 Cache	92
Appendix B	93
Values Returned by the CPUID Instruction	93