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AMD AMD-K6-2/450 Design Guide - Page 70

Testing for the CPUID Instruction, Illegal Instruction Exception Method, EFLAGS IDBit Method

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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 s Standard functions provide a simple method for software to access information common to all x86 processors. s Extended functions provide information on extensions specific to a vendor's processor (for example, AMD's processors). The flexibility of the CPUID instruction allows for the addition of new CPUID functions in future generations of processors. "Appendix A" on page 71 contains a detailed description of the CPUID instruction. Testing for the CPUID Instruction Illegal Instruction Exception Method EFLAGS ID-Bit Method Beginning with the AMD-K6E processor Model 7, all AMD processors support the CPUID instruction. However, it is still recommended that software verify that the CPUID instruction is supported. To use the CPUID instruction, software must first determine if the processor supports the CPUID instruction. CPUID support is determined in one of the following ways: s Execute the CPUID instruction and check whether an illegal instruction exception occurs. If an exception occurs, the processor does not have CPUID support. s Check if the ID bit (bit 21) of the EFLAGS register is writable. If the bit is writable (that is, it can be modified), the CPUID instruction is supported. The operating system (OS) environment determines which approach is more appropriate. These techniques are described in the following sections. This technique requires a way for a user program to detect and handle illegal instruction exceptions. Where such capabilities are present, this method represents a reliable way of detecting support for the CPUID instruction. The CPUID sample code described on page 67 uses this approach. This technique retrieves the contents of EFLAGS using the PUSHFD instruction, toggles the ID bit, and uses the POPFD instruction to write the modified value of the ID bit into the EFLAGS register. It then retrieves the contents of EFLAGS using a second PUSHFD instruction and checks whether the value of the ID bit differs from the original value. 58 Embedded AMD Processor Recognition

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
Introduction	13
Audience	13
Processor Models and Steppings	14
AMDK6™E Embedded Processor	15
Model 7	15
AMDK6™2 Processor	15
Model 8/[7:0]	15
Model 8/[F:8]	15
AMDK6™2E Embedded Processor	16
Model 8/[F:8]	16
AMDK6™2E+ Embedded Processor	16
Model D/[7:4]	16
AMDK6™III Processor	17
Model 9/[3:0]	17
AMDK6™IIIE+ Embedded Processor	17
Model D/[3:0]	17
BIOS Consideration Checklist	18
CPUID	18
CPU Speed Detection	18
ModelSpecific Registers (MSRs)	18
Cache Testing	19
SMM Issues	19
States after RESET and INIT	20
Register States after RESET and INIT	20
Processor State after INIT	21
BuiltIn SelfTest (BIST)	22
CPUID Identification Algorithms	23
System Management Mode (SMM)	25
StateSave Map Differences	25
I/O Trap Dword Differences	25
ModelSpecific Registers Overview	26
Standard Model-Specific Registers (All Models)	28
MachineCheck Address Register (MCAR) and MachineCheck Type Register (MCTR)	28
Test Register 12 (TR12)	28
Time Stamp Counter (TSC)	28
Model 7 and Model 8/[7:0] Registers	29
Extended Feature Enable Register (EFER)	30
Write Handling Control Register (WHCR)	31
Write Allocation	31
Write Cacheability Detection Enable Bit	32
Write Allocate Enable Limit Field	32
Write Allocate Enable 15to16Mbyte Field.	33
SYSCALL/SYSRET Target Address Register (STAR)	34
Model 8/[F:8] Registers	35
Extended Feature Enable Register (EFER)	36
External Write Buffer Empty Control Field	36
Write Handling Control Register (WHCR)	39
Write Allocation	39
Write Allocate Enable Limit Field	40
Write Allocate Enable 15to16Mbyte Field	41
UC/WC Cacheability Control Register (UWCCR)	42
Physical Base Address n (n=0, 1)	43
Physical Address Mask n (n=0, 1)	43
WCn (n=0, 1)	43
UCn (n=0, 1)	43
Memory-Range Restrictions	44
Examples	45
Processor State Observability Register (PSOR)	46
NOL2 Bit	46
STEP Field	46
BF Field	46
Page Flush/Invalidate Register (PFIR)	48
LINPAGE Field	48
PF Bit	48
F/I Bit	49
Model 9 Registers	50
Extended Feature Enable Register (EFER)	51
Level-2 Cache Array Access Register (L2AAR)	52
LRU (Least Recently Used) Field	55
Writing to L2 Tag of AMDK6™III Processor	55
Model D Registers	57
Processor State Observability Register (PSOR) (Low-Power Versions)	58
PBF[2:0] Field	58
VID Field	58
NOL2 Bit	59
STEP Field	59
EBF[2:0] Field	59
Level-2 Cache Array Access Register (L2AAR)	60
LRU (Least Recently Used) Field	64
Writing to L2 Tag of AMDK6IIIE+ Processor	65
Enhanced Power Management Register (EPMR) (Low-Power Versions)	66
EPM 16-Byte I/O Block (Low-Power Versions Only)	67
BVC Field	67
Embedded AMD Processor Recognition	69
CPUID Instruction Overview	69
Testing for the CPUID Instruction	70
Illegal Instruction Exception Method	70
EFLAGS IDBit Method	70
Using CPUID Functions	71
Identifying the Processor’s Vendor	72
Testing For Extended Functions	73
Determining the Processor Signature	73
Identifying Supported Features	75
Determining Instruction Set Support	76
Detection Algorithm for Determining Instruction Set Support	77
CPUID Test	77
Standard Function Test	77
MMX™ Test	77
Optional SSE Test	77
Extended Functions Test	77
3DNow!™ Test	77
Vendor Check	77
3DNow! Extensions Test	78
AMD Multimedia Instruction Extensions Test	78
AMD Processor Signature (Extended Function)	78
Displaying the Processor’s Name	78
Displaying Cache Information	79
Determining AMDPowerNow!™ Technology Information	79
Sample Code	79
New AMDK6™ Processor Instructions	80
Additional Considerations	81
Software Timing Dependencies Relative to Memory Controller Setup	81
Pipelining Support	81
Read-Only Memory	82
Appendix A	83
CPUID	83
Standard Functions	84
Extended Functions	87
Cache Associativity Field Definitions	92
Associativity for L1 Caches and L1 TLBs	92
Associativity for L2 Cache	92
Appendix B	93
Values Returned by the CPUID Instruction	93

Match case Limit results 1 per page

Embedded AMD Processor Recognition

Embedded AMD-K6™ Processors BIOS Design Guide

23913A/0—November 2000

Preliminary Information

■

Standard functions

provide a simple method for software to

access information common to all x86 processors.

■

Extended functions

provide information on extensions

specific to a vendor’s processor (for example, AMD’s

processors).

The flexibility of the CPUID instruction allows for the addition

of new CPUID functions in future generations of processors.

“Appendix A” on page 71 contains a detailed description of the

CPUID instruction.

Testing for the CPUID Instruction

Beginning with the AMD-K6E processor Model 7, all AMD

processors support the CPUID instruction. However, it is still

recommended that software verify that the CPUID instruction

is supported. To use the CPUID instruction, software must first

determine if the processor supports the CPUID instruction.

CPUID support is determined in one of the following ways:

■

Execute the CPUID instruction and check whether an

illegal instruction exception occurs. If an exception occurs,

the processor does not have CPUID support.

■

Check if the ID bit (bit 21) of the EFLAGS register is

writable. If the bit is writable (that is, it can be modified),

the CPUID instruction is supported.

The operating system (OS) environment determines which

approach is more appropriate. These techniques are described

in the following sections.

Illegal Instruction

Exception Method

This technique requires a way for a user program to detect and

handle illegal instruction exceptions. Where such capabilities

are present, this method represents a reliable way of detecting

support for the CPUID instruction. The CPUID sample code

described on page 67 uses this approach.

EFLAGS ID-Bit

Method

This technique retrieves the contents of EFLAGS using the

PUSHFD instruction, toggles the ID bit, and uses the POPFD

instruction to write the modified value of the ID bit into the

EFLAGS register. It then retrieves the contents of EFLAGS

using a second PUSHFD instruction and checks whether the

value of the ID bit differs from the original value.

AMD AMD-K6-2/450 Design Guide - Page 70

Testing for the CPUID Instruction, Illegal Instruction Exception Method, EFLAGS IDBit Method

Page 70 highlights

Testing for the CPUID Instruction, Illegal Instruction Exception Method, EFLAGS IDBit Method