AMD AMD-K6-2/450 Design Guide - Page 41

Write Allocate Enable 15to16Mbyte Field

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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Write Allocate Enable 15-to-16-Mbyte Field The WAE15M bit is used to enable write allocations for the memory write cycles that address the 1 Mbyte of memory between 15 Mbytes and 16 Mbytes. This bit must be set to 1 to allow write allocates in this memory area. This sub-mechanism of the WAELIM provides a memory hole to prevent write allocates. This memory hole is provided to account for a small number of uncommon memory-mapped I/O adapters that use this particular memory address space. If the system contains one of these peripherals, the bit should be set to 0 (even if the WAE15M bit is set to 0, write allocates can still occur between 15 Mbytes and 16 Mbytes due to the "Write to a Cacheable Page" and "Write to a Sector" mechanisms). The WAE15M bit is ignored if the value in the WAELIM field is set to less than 16 Mbytes. By definition, write allocations are not performed in the memory area between 640 Kbytes and 1 Mbyte unless the processor determines a pending write cycle is cacheable by means of "Write to a Cacheable Page" or "Write to a Sector." It is not safe to perform write allocations between 640 Kbytes and 1 Mbyte (000A_0000h to 000F_FFFFh) because it is considered a noncacheable region of memory. Additionally, if a memory region is defined as write-combinable or uncacheable by a MTRR, write allocates are not performed in that region. Model 8/[F:8] Registers 29

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Model 8/[F:8] Registers
29
23913A/0—November 2000
Embedded AMD-K6™ Processors BIOS Design Guide
Preliminary Information
Write Allocate Enable
15-to-16-Mbyte Field
The WAE15M bit is used to enable write allocations for the
memory write cycles that address the 1 Mbyte of memory
between 15 Mbytes and 16 Mbytes. This bit must be set to 1 to
allow write allocates in this memory area.
This sub-mechanism of the WAELIM provides a memory hole to
prevent write allocates. This memory hole is provided to
account for a small number of uncommon memory-mapped I/O
adapters that use this particular memory address space. If the
system contains one of these peripherals, the bit should be set
to 0 (even if the WAE15M bit is set to 0, write allocates can still
occur between 15 Mbytes and 16 Mbytes due to the “Write to a
Cacheable Page” and “Write to a Sector” mechanisms). The
WAE15M bit is ignored if the value in the WAELIM field is set
to less than 16 Mbytes.
By definition, write allocations are not performed in the
memory area between 640 Kbytes and 1 Mbyte unless the
processor determines a pending write cycle is cacheable by
means of “Write to a Cacheable Page” or “Write to a Sector.” It
is not safe to perform write allocations between 640 Kbytes and
1 Mbyte (000A_0000h to 000F_FFFFh) because it is considered
a noncacheable region of memory. Additionally, if a memory
region is defined as write-combinable or uncacheable by a
MTRR, write allocates are not performed in that region.