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AMD AMD-K6-2/450 Design Guide - Page 51

Extended Feature Enable Register (EFER), EFER register. The EFER register is MSR C000_0080h.

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23913A/0-November 2000 Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide Extended Feature Enable Register (EFER) Figure 10 shows the format of the EFER register for models 9 and D, and Table 20 defines the function of each bit of the EFER register. The EFER register is MSR C000_0080h. Note: Bits 3:0 of the EFER register in models 9 and D are identical to the implementation of these bits in Model 8/[F:8]. For models 9 and D, the L2 Disable bit (L2D), EFER[4], is added. The complete new register description is included in this section. 63 5 4 3 21 0 L DS 2 EWBEC P C D EE Reserved Symbol Description Bit L2D L2 Disable 4 EWBEC EWBE Control 3-2 DPE Data Prefetch Enable 1 SCE System Call Extension 0 Figure 10. Extended Feature Enable Register (EFER) (Models 9 and D) Table 20. Extended Feature Enable Register (EFER) Definition (Models 9 and D) Bit Description R/W Function 63-5 Reserved R Writing a 1 to any reserved bit causes a general protection fault to occur. All reserved bits are always read as 0. 4 L2 Disable (L2D) If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for R/W debug and testing purposes. For normal operation and maximum performance, this bit must be set to 0 (this is the default setting following reset). 3-2 EWBE Control (EWBEC) This 2-bit field controls the behavior of the processor with respect to the ordering R/W of write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE# Disable (GEWBED) and Speculative EWBE# Disable (SEWBED), respectively. DPE must be set to 1 to enable data prefetching (this is the default setting follow- 1 Data Prefetch Enable (DPE) R/W ing reset). If enabled, cache misses initiated by a memory read within a 32-byte cache line are conditionally followed by cache-line fetches of the other line in the 64-byte sector. 0 System Call Extension (SCE) R/W SCE must be set to 1 to enable usage of the SYSCALL and SYSRET instructions. Note: Setting L2D to 1 does not guarantee cache coherency. To ensure coherency, the processor's caches must be disabled (by setting the CD bit of the CR0 register to 1), then flushed prior to setting L2D to 1. Model 9 Registers 39

Section	Page
Contents	3
List of Figures	7
List of Tables	9
Revision History	11
Introduction	13
Audience	13
Processor Models and Steppings	14
AMDK6™E Embedded Processor	15
Model 7	15
AMDK6™2 Processor	15
Model 8/[7:0]	15
Model 8/[F:8]	15
AMDK6™2E Embedded Processor	16
Model 8/[F:8]	16
AMDK6™2E+ Embedded Processor	16
Model D/[7:4]	16
AMDK6™III Processor	17
Model 9/[3:0]	17
AMDK6™IIIE+ Embedded Processor	17
Model D/[3:0]	17
BIOS Consideration Checklist	18
CPUID	18
CPU Speed Detection	18
ModelSpecific Registers (MSRs)	18
Cache Testing	19
SMM Issues	19
States after RESET and INIT	20
Register States after RESET and INIT	20
Processor State after INIT	21
BuiltIn SelfTest (BIST)	22
CPUID Identification Algorithms	23
System Management Mode (SMM)	25
StateSave Map Differences	25
I/O Trap Dword Differences	25
ModelSpecific Registers Overview	26
Standard Model-Specific Registers (All Models)	28
MachineCheck Address Register (MCAR) and MachineCheck Type Register (MCTR)	28
Test Register 12 (TR12)	28
Time Stamp Counter (TSC)	28
Model 7 and Model 8/[7:0] Registers	29
Extended Feature Enable Register (EFER)	30
Write Handling Control Register (WHCR)	31
Write Allocation	31
Write Cacheability Detection Enable Bit	32
Write Allocate Enable Limit Field	32
Write Allocate Enable 15to16Mbyte Field.	33
SYSCALL/SYSRET Target Address Register (STAR)	34
Model 8/[F:8] Registers	35
Extended Feature Enable Register (EFER)	36
External Write Buffer Empty Control Field	36
Write Handling Control Register (WHCR)	39
Write Allocation	39
Write Allocate Enable Limit Field	40
Write Allocate Enable 15to16Mbyte Field	41
UC/WC Cacheability Control Register (UWCCR)	42
Physical Base Address n (n=0, 1)	43
Physical Address Mask n (n=0, 1)	43
WCn (n=0, 1)	43
UCn (n=0, 1)	43
Memory-Range Restrictions	44
Examples	45
Processor State Observability Register (PSOR)	46
NOL2 Bit	46
STEP Field	46
BF Field	46
Page Flush/Invalidate Register (PFIR)	48
LINPAGE Field	48
PF Bit	48
F/I Bit	49
Model 9 Registers	50
Extended Feature Enable Register (EFER)	51
Level-2 Cache Array Access Register (L2AAR)	52
LRU (Least Recently Used) Field	55
Writing to L2 Tag of AMDK6™III Processor	55
Model D Registers	57
Processor State Observability Register (PSOR) (Low-Power Versions)	58
PBF[2:0] Field	58
VID Field	58
NOL2 Bit	59
STEP Field	59
EBF[2:0] Field	59
Level-2 Cache Array Access Register (L2AAR)	60
LRU (Least Recently Used) Field	64
Writing to L2 Tag of AMDK6IIIE+ Processor	65
Enhanced Power Management Register (EPMR) (Low-Power Versions)	66
EPM 16-Byte I/O Block (Low-Power Versions Only)	67
BVC Field	67
Embedded AMD Processor Recognition	69
CPUID Instruction Overview	69
Testing for the CPUID Instruction	70
Illegal Instruction Exception Method	70
EFLAGS IDBit Method	70
Using CPUID Functions	71
Identifying the Processor’s Vendor	72
Testing For Extended Functions	73
Determining the Processor Signature	73
Identifying Supported Features	75
Determining Instruction Set Support	76
Detection Algorithm for Determining Instruction Set Support	77
CPUID Test	77
Standard Function Test	77
MMX™ Test	77
Optional SSE Test	77
Extended Functions Test	77
3DNow!™ Test	77
Vendor Check	77
3DNow! Extensions Test	78
AMD Multimedia Instruction Extensions Test	78
AMD Processor Signature (Extended Function)	78
Displaying the Processor’s Name	78
Displaying Cache Information	79
Determining AMDPowerNow!™ Technology Information	79
Sample Code	79
New AMDK6™ Processor Instructions	80
Additional Considerations	81
Software Timing Dependencies Relative to Memory Controller Setup	81
Pipelining Support	81
Read-Only Memory	82
Appendix A	83
CPUID	83
Standard Functions	84
Extended Functions	87
Cache Associativity Field Definitions	92
Associativity for L1 Caches and L1 TLBs	92
Associativity for L2 Cache	92
Appendix B	93
Values Returned by the CPUID Instruction	93

Match case Limit results 1 per page

Model 9 Registers

23913A/0—November 2000

Embedded AMD-K6™ Processors BIOS Design Guide

Preliminary Information

Extended Feature Enable Register (EFER)

Figure 10 shows the format of the EFER register for models 9

and D, and Table 20 defines the function of each bit of the

EFER register. The EFER register is MSR C000_0080h.

Note:

Bits 3:0 of the EFER register in models 9 and D are identical

to the implementation of these bits in Model 8/[F:8]. For

models 9 and D, the L2 Disable bit (L2D), EFER[4], is

added. The complete new register description is included in

this section.

Figure 10.

Extended Feature Enable Register (EFER) (Models 9 and D)

Note:

Setting L2D to 1 does not guarantee cache coherency. To

ensure coherency, the processor’s caches must be disabled

(by setting the CD bit of the CR0 register to 1), then flushed

prior to setting L2D to 1.

Table 20.

Extended Feature Enable Register (EFER) Definition (Models 9 and D)

Bit

Description

R/W Function

63–5

Reserved

Writing a 1 to any reserved bit causes a general protection fault to occur. All

reserved bits are always read as 0.

L2 Disable (L2D)

R/W

If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for

debug and testing purposes. For normal operation and maximum performance,

this bit must be set to 0 (this is the default setting following reset).

3-2

EWBE Control (EWBEC)

R/W

This 2-bit field controls the behavior of the processor with respect to the ordering

of write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE#

Disable (GEWBED) and Speculative EWBE# Disable (SEWBED), respectively.

Data Prefetch Enable (DPE)

R/W

DPE must be set to 1 to enable data prefetching (this is the default setting follow-

ing reset). If enabled, cache misses initiated by a memory read within a 32-byte

cache line are conditionally followed by cache-line fetches of the other line in the

64-byte sector.

System Call Extension (SCE)

R/W

SCE must be set to 1 to enable usage of the SYSCALL and SYSRET instructions.

Reserved

EWBEC

Symbol

Description

Bit

L2D

L2 Disable

EWBEC

EWBE Control

3-2

DPE

Data Prefetch Enable

SCE

System Call Extension