AMD AMD-K6-2/450 Design Guide - Page 60
Level-2 Cache Array Access Register (L2AAR), Each sector contains two 32-byte cache lines
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Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 Level-2 Cache Array Access Register (L2AAR) Model D also provides the L2AAR register that allows for direct access to the L2 cache and L2 tag arrays. Note: The L2AAR register is identical to the Model 9 implementation. Some information in this section is duplicated to account for the different L2 cache sizes in the AMD-K6-2E+ and AMD-K6-IIIE+ processors. The L2 cache in the AMD-K6-2E+ and AMD-K6-IIIE+ processors is organized as shown in Figure 18: s Four 32-Kbyte ways (AMD-K6-2E+ processor) or four 64Kbyte ways (AMD-K6-IIIE+ processor) s Each way contains 512 (AMD-K6-2E+ processor) or 1024 (AMD-K6-IIIE+ processor) sets s Each set contains four 64-byte sectors (one sector in each way) s Each sector contains two 32-byte cache lines s Each cache line contains four 8-byte octets s Each octet contains an upper and lower dword (4 bytes) Each line within a sector contains its own MESI state bits, and associated with each sector is a tag and LRU (Least Recently Used) information. Set 0 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU 64 bytes Line1/MESI Line0/MESI Tag/LRU Way 0 Way 1 Way 2 Way 3 512 or 1024 sets Set 1023 Figure 18. L2 Cache Organization 48 Model D Registers