AMD AMD-K6-2/450 Design Guide - Page 32

Preliminary Information Embedded AMD-K6™ Processors BIOS Design Guide 23913A/0-November 2000 63 987 0 Reserved Symbol WCDE WAELIM WAE15M Description Bits Always program to 0 8 Write Allocate Enable Limit 7-1 Write Allocate Enable 15-to-16-Mbyte 0 Note: Hardware RESET initializes this MSR to all zeros. Figure 3. Write Handling Control Register (WHCR) (Models 7 and 8/[7:0]) WAELIM 10 W A E 1 5 M Write Cacheability Detection Enable Bit For proper functionality, always program bit 8 of WHCR to 0. See "Pipelining Support" on page 69 for more information on the WCDE bit. Write Allocate Enable Limit Field The WAELIM field is 7 bits wide. This field, multiplied by 4 Mbytes, defines an upper memory limit. Any pending write cycle that misses the L1 cache and that addresses memory below this limit causes the processor to perform a write allocate (assuming the address is not within a range where write allocates are disallowed). Write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write allocate mechanisms - "Write to a Cacheable Page" and "Write to a Sector" (for more information, see the "Cache Organization" chapter in the appropriate AMD-K6 or AMD-K6E processor data sheet. The maximum value of this limit is ((27-1) · 4 Mbytes) = 508 Mbytes. When all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled (even if all bits in the WAELIM field are set to 0, write allocates can still occur due to the "Write to a Cacheable Page" and "Write to a Sector" mechanisms). Once the BIOS determines the amount of RAM installed in the system, this number should also be used to program the WAELIM field. For example, a system with 32 Mbytes of RAM would program the WAELIM field with the value 0001000b. 20 Model 7 and Model 8/[7:0] Registers