Epson TM U200D Technical Reference - Page 60

CPU pin functions, Function, Signal Name, Level, Description - software

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TM-U200D/U200PD Technical Manual CPU pin functions Pin CPU No. Function Signal Name I/O 9 P62 NE I 10 P63 DK S I 11 P64 RE I 12 P65 HP DTC I 13 P66 DET I 14 P67 AC RST I 15 VCC VCC I 16 P70 CTS I 17 P71 CCE O 18 P72/RXD1 RD I 19 P73/CLK1 CLK IN/DTR I/O 20 P74/TXD1 SD O 21 RESET RESET I 22 CLK CLK O 23 VSS VSS I 24 X1 X1 I 25 X2 X2 O 26 EA EA I 27 P75 28 P76 29 P77 P75 (A16) O P76 (A17) O P77 (A18) O 30 P80 WDTOUT O 31 P81/INT0 32 P82 CLK IN/DTR I PF SW I 33 ALE ALE O 34 VCC VCC I Level TTL TTL TTL TTL TTL TTL (+5V) TTL TTL TTL TTL TTL --TTL (0V) ----TTL TTL TTL TTL TTL TTL TTL TTL (+5V) Description Paper roll near-end detection Low: no paper High: paper present Drawer open/close Low: open Paper roll end detection Low: paper present High: no paper Carriage Detector low: home position Host interface DET Auto cutter position detection (reset) Main power terminal Host interface CTS Low: on 4M ROM CE signal Low: active Host interface RD Low:on Host interface CLK IN/DTR Host interface SD Low: on CPU reset input Low: on Not used. Open GND terminal Connected to ceramic vibration generator. f=14.74MHz ± 0.5% Connected to ceramic. f=14.74MHz ± 0.5% External memory access Low: external ROM High: internal ROM (CPU mask) External memory address A16 (software) External memory address A17 (software) External memory address A18 (software) Watch dog timer error (and hardware limited time power supply switch) Low: error (reset) Connected to pin #19 Paper feed switch Low: active Address latch enable signal Latch address on the bus AD0 to AD7 at falling. Main power terminal (+5V) Rev. B Mechanism Configuration and Operating Principles

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Rev. B
Mechanism Configuration and Operating Principles
TM-U200D/U200PD Technical Manual
9
P62
NE
I
TTL
Paper roll near-end detection Low: no paper
High: paper present
10
P63
DK S
I
TTL
Drawer open/close Low: open
11
P64
RE
I
TTL
Paper roll end detection Low: paper present
High: no paper
12
P65
HP DTC
I
TTL
Carriage Detector
low: home position
13
P66
DET
I
TTL
Host interface DET
14
P67
AC RST
I
TTL
Auto cutter position detection (reset)
15
VCC
VCC
I
(+5V)
Main power terminal
16
P70
CTS
I
TTL
Host interface CTS Low: on
17
P71
CCE
O
TTL
4M ROM CE signal Low: active
18
P72/RXD1
RD
I
TTL
Host interface RD Low:on
19
P73/CLK1
CLK IN/DTR
I/O
TTL
Host interface CLK IN/DTR
20
P74/TXD1
SD
O
TTL
Host interface SD Low: on
21
RESET
RESET
I
---
CPU reset input Low: on
22
CLK
CLK
O
TTL
Not used. Open
23
VSS
VSS
I
(0V)
GND terminal
24
X1
X1
I
---
Connected to ceramic vibration generator.
f=14.74MHz ± 0.5%
25
X2
X2
O
---
Connected to ceramic. f=14.74MHz ± 0.5%
26
EA
EA
I
TTL
External memory access Low: external ROM
High: internal ROM (CPU mask)
27
P75
P75 (A16)
O
TTL
External memory address A16 (software)
28
P76
P76 (A17)
O
TTL
External memory address A17 (software)
29
P77
P77 (A18)
O
TTL
External memory address A18 (software)
30
P80
WDTOUT
O
TTL
Watch dog timer error (and hardware limited
time power supply switch) Low: error (reset)
31
P81/INT0
CLK IN/DTR
I
TTL
Connected to pin #19
32
P82
PF SW
I
TTL
Paper feed switch Low: active
33
ALE
ALE
O
TTL
Address latch enable signal
Latch address on the bus AD0 to AD7 at falling.
34
VCC
VCC
I
(+5V)
Main power terminal (+5V)
CPU pin functions
Pin
No.
CPU
Function
Signal Name
I/O
Level
Description