Epson TM U200D Technical Reference - Page 61

Function, Signal Name, Level, Description

Page 61 highlights

CPU pin functions Pin CPU No. Function Signal Name 35 AD0 AD0 36 AD1 AD1 37 AD2 AD2 38 AD3 AD3 39 AD4 AD4 40 AD5 AD5 41 AD6 AD6 42 AD7 AD7 43 A8 A8 44 A9 A9 45 A10 A10 46 A11 A11 47 A12 A12 48 A13 A13 49 A14 A14 50 A15 A15 51 VSS VSS 52 P20 CR A/DSW1 53 P21 CR B/DSW2 54 P22 CR C/DSW3 55 P23 CR D/DSW4 56 P90 PF A/DSW5 57 P91 PF B/DSW6 58 P92 PF C/DSW7 59 P93 PF D/DSW8 60 RD RD 61 WR WR 62 P32 DKD1 63 P33 DKD2 64 P40 HEAD8 65 P41 HEAD7 66 P42 HEAD6 67 P43 HEAD5 68 P44 HEAD4 69 P45 HEAD3 I/O Level 3 state TTL O TTL I (0V) I/O TTL I/O TTL O TTL O TTL O TTL O TTL O TTL O TTL O TTL O TTL O TTL O TTL Description Address/data bus Transmit address (lower 8 bits) and data. Address bus (address upper 8 bits) GND terminal Motor, carriage drive control 2-2 phase excitation All the terminals on (low): hold DIP SW 1-1to 1-4 read when P100, P101 is low Motor, paper feed drive control 2-2 phase excitation All the terminals on (low): hold DIP SW 1-5 to 1-8 read when P100, P101 is low External memory data read signal External memory data write signal Drawer kick-out drive signal 1 Low: active Drawer kick-out drive signal 2 Low: active Print head #8 drive signal Low: on Print head #7 drive signal Low: on Print head #6 drive signal Low: on Print head #5 drive signal Low: on Print head #4 drive signal Low: on Print head #3 drive signal Low: on 2-20 Mechanism Configuration and Operating Principles Rev.B

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2-20
Mechanism Configuration and Operating Principles
Rev.B
35
AD0
AD0
3 state
TTL
Address/data bus
Transmit address (lower 8 bits) and data.
36
AD1
AD1
37
AD2
AD2
38
AD3
AD3
39
AD4
AD4
40
AD5
AD5
41
AD6
AD6
42
AD7
AD7
43
A8
A8
O
TTL
Address bus (address upper 8 bits)
44
A9
A9
45
A10
A10
46
A11
A11
47
A12
A12
48
A13
A13
49
A14
A14
50
A15
A15
51
VSS
VSS
I
(0V)
GND terminal
52
P20
CR A/DSW1
I/O
TTL
Motor, carriage drive control 2-2 phase
excitation All the terminals on (low): hold
DIP SW 1-1to 1-4 read when P100, P101 is low
53
P21
CR B/DSW2
54
P22
CR C/DSW3
55
P23
CR D/DSW4
56
P90
PF A/DSW5
I/O
TTL
Motor, paper feed drive control 2-2 phase
excitation All the terminals on (low): hold
DIP SW 1-5 to 1-8 read when P100, P101 is low
57
P91
PF B/DSW6
58
P92
PF C/DSW7
59
P93
PF D/DSW8
60
RD
RD
O
TTL
External memory data read signal
61
WR
WR
O
TTL
External memory data write signal
62
P32
DKD1
O
TTL
Drawer kick-out drive signal 1 Low: active
63
P33
DKD2
O
TTL
Drawer kick-out drive signal 2 Low: active
64
P40
HEAD8
O
TTL
Print head #8 drive signal Low: on
65
P41
HEAD7
O
TTL
Print head #7 drive signal Low: on
66
P42
HEAD6
O
TTL
Print head #6 drive signal Low: on
67
P43
HEAD5
O
TTL
Print head #5 drive signal Low: on
68
P44
HEAD4
O
TTL
Print head #4 drive signal Low: on
69
P45
HEAD3
O
TTL
Print head #3 drive signal Low: on
CPU pin functions
Pin
No.
CPU
Function
Signal Name
I/O
Level
Description