Epson EPL-N1200 Service Manual - Page 79

MB86930, E05A91, Reset Circuit, Bus Control Circuit

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Operating Principles EPL-N1200 Service Manual 2.2.1.1 Reset Circuit The entire system (CPU and external devices) can be initialized if the RESET signal (CPU pin 113) is active simultaneously. This circuit uses an M5193B IC to monitor the supply voltage if the voltage level less than 4.25 V is detected. The reset time is approximately 128 ms. +5V +5V Vcc OUT M51953B (IC2) C RSTIN RSTOUT E05B31 (IC38) RESET Figure 2-29. Reset Circuit 2.2.1.2 Bus Control Circuit The MB86930 CPU outputs the R/W (read/write) signal, AS (address strobe) signal, and the BE0, BE1, BE2, and BE3 signals (byte enables) to the ASIC E05A91. The ASIC E05A91 uses these signals to generate the RD (read strobe) signal, WR (write strobe) signal, and READY signal. CPU MB86930 (IC15) R/W AS BE0-3 READY E05A91 (IC1) Address Data RD WR Bus Bus Figure 2-30. Bus Control Circuit 2-20 Rev. A

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2.2.1.1 Reset Circuit
The entire system (CPU and external devices) can be initialized if the
RESET signal (CPU pin 113)
is active simultaneously. This circuit uses an M5193B IC to monitor the supply voltage if
the voltage
level less than 4.25 V is detected.
The reset time is approximately 128 ms.
2.2.1.2 Bus Control Circuit
The MB86930 CPU outputs the R/
W (read/write) signal,
AS (address strobe) signal, and the
BE0,
BE1,
BE2, and
BE3 signals (byte enables) to the ASIC E05A91.
The ASIC E05A91 uses these
signals to generate the
RD (read strobe) signal,
WR (write strobe) signal, and
READY signal.
+5V
Vcc
C
OUT
+5V
M51953B
(IC2)
RESET
RSTOUT
RSTIN
E05B31
(IC38)
Figure 2-29. Reset Circuit
R/W
AS
BE0-3
RD
WR
READY
Data
Bus
Address
Bus
CPU
MB86930
(IC15)
E05A91
(IC1)
Figure 2-30. Bus Control Circuit
Operating Principles
EPL-N1200 Service Manual
2-20
Rev. A