Epson EPL-N1200 Service Manual - Page 80

E05A91, DRAM Management

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EPL-N1200 Service Manual Operating Principles 2.2.1.3 Interrupt Control The ASIC E05A93 determines the priority level of the interrupt and outputs it to terminals IRL0 IRL3. Then an interrupt is sent to the CPU. When the IRL0-3 value is 1111B, the CPU process is a non-maskable interrupt process. When the IRL0-3 value is 0000B, the CPU process is a standard process. When the IRL0-3 is any other value, the CPU process is a maskable interrupt process. 2.2.1.4 DRAM Management The video controller uses DRAMs for the system RAM and for the V-RAM. In this printer, four standard 512K × 8bit DRAMs are mounted in locations IC18, IC19, IC20, and IC21, providing a total of 2 MB. SIMM sockets number 1 (CN1) and number 2 (CN6) are optional SIMM sockets. These SIMM sockets can use 1, 2, 4, 8, 16, 32 MB SIMM (32-bit bus). The DRAMs (including optional SIMMs) are managed by the ASIC E05A91, which also outputs MA0-10 (memory address), RAS/CAS, and DWE signals. RAS3,4 RAS1,2 RAS0 DWE E05A91 (IC1) CAS0,1,2,3 MA0-10 DRAM (IC18) DRAM (IC19) DRAM (IC20) DRAM (IC21) SIMM Slot 1 (CN1) CPU DATA BUS Figure 2-31. DRAM Management SIMM Slot 2 (CN6) Rev. A 2-21

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2.2.1.3
Interrupt Control
The ASIC E05A93 determines the priority level of the interrupt and outputs it to terminals IRL0 -
IRL3. Then an interrupt is sent to the CPU. When the IRL0-3 value is 1111B, the CPU process is a
non-maskable interrupt process. When the IRL0-3 value is 0000B, the CPU process is a standard
process. When the IRL0-3 is any other value, the CPU process is a maskable interrupt process.
2.2.1.4
DRAM Management
The video controller uses DRAMs for the system RAM and for the V-RAM.
In this printer, four standard 512K
×
8bit
DRAMs are mounted in locations IC18, IC19, IC20, and
IC21, providing a total of 2 MB. SIMM sockets number 1 (CN1) and number 2 (CN6) are optional
SIMM sockets. These SIMM sockets can use 1, 2, 4, 8, 16, 32 MB SIMM (32-bit bus).
The DRAMs (including optional SIMMs) are managed by the ASIC E05A91, which also outputs
MA0-10 (memory address),
RAS/
CAS, and
DWE signals.
CAS0,1,2,3
DRAM
(IC18)
DRAM
(IC19)
DRAM
(IC20)
DRAM
(IC21)
DWE
RAS0
RAS1,2
RAS3,4
MA0-10
CPU DATA BUS
SIMM
Slot 1
(CN1)
SIMM
Slot 2
(CN6)
E05A91
(IC1)
Figure 2-31. DRAM Management
EPL-N1200 Service Manual
Operating Principles
Rev. A
2-21