IBM 2109 Service Guide - Page 107

Appendix B. Diagnostics, Diagnostic overview, Isolating a system fault, Removing power

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Appendix B. Diagnostics This appendix describes the diagnostic tests and their results on the 2109 Model S16 Switch. Diagnostic overview The switch is designed for maintenance-free operation. When a suspected failure occurs, the switch has self-diagnostic capabilities to aid in isolating any equipment or fabric failures. The switch supports POSTs and diagnostic tests. The diagnostic tests determine the status of the switch, and then isolates any problems. Telnet commands determine the status of the switches, any error conditions, and the operating statistics of the switches. Attention: Many of the tests are disruptive to switch operation. Read the information about each diagnostic test before beginning a diagnostic test or procedure. Isolating a system fault Various loopback paths are built into the switch hardware for diagnostic purposes. A loopback path test within the switch verifies the proper internal fibre-channel port logic functions and the paths between the interfaces and central memory. The switch diagnostics also support external loops that include the system board and their GBIC modules in cross-port configurations. These port-to-port diagnostics allow you to check installed fibre-channel cables and to perform port fault isolation. Removing power After all data transferring processes that are external to the switch are complete, the removal of power from the switch does not disrupt the fabric. Note: Error messages are stored in RAM and are lost when power is removed from the switch. Access the error message log to view and note any error messages before removing power from the switch. Service action for error messages See the "Diagnostic error messages" on page 122 for the appropriate service action for each message. POST tests Table 27 lists the diagnostic tests that are automatically run during a POST. Table 27. POST tests Test Description Memory test Port register test Checks CPU RAM memory Checks the ASIC registers and SRAMs Central memory test CMI conn test Checks the system board SRAMs Checks the CMI bus between ASICs © Copyright IBM Corp. 1999, 2000 91

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Appendix B. Diagnostics
This appendix describes the diagnostic tests and their results on the 2109 Model
S16 Switch.
Diagnostic overview
The switch is designed for maintenance-free operation. When a suspected failure
occurs, the switch has self-diagnostic capabilities to aid in isolating any equipment
or fabric failures.
The switch supports POSTs and diagnostic tests. The diagnostic tests determine
the status of the switch, and then isolates any problems.
Telnet commands determine the status of the switches, any error conditions, and
the operating statistics of the switches.
Attention:
Many of the tests are disruptive to switch operation. Read the
information about each diagnostic test before beginning a diagnostic test or
procedure.
Isolating a system fault
Various loopback paths are built into the switch hardware for diagnostic purposes. A
loopback path test within the switch verifies the proper internal fibre-channel port
logic functions and the paths between the interfaces and central memory.
The switch diagnostics also support external loops that include the system board
and their GBIC modules in cross-port configurations. These port-to-port diagnostics
allow you to check installed fibre-channel cables and to perform port fault isolation.
Removing power
After all data transferring processes that are external to the switch are complete,
the removal of power from the switch does not disrupt the fabric.
Note:
Error messages are stored in RAM and are lost when power is removed
from the switch. Access the error message log to view and note any error
messages before removing power from the switch.
Service action for error messages
See the “Diagnostic error messages” on page 122 for the appropriate service action
for each message.
POST tests
Table27 lists the diagnostic tests that are automatically run during a POST.
Table 27. POST tests
Test
Description
Memory test
Checks CPU RAM memory
Port register test
Checks the ASIC registers and SRAMs
Central memory test
Checks the system board SRAMs
CMI conn test
Checks the CMI bus between ASICs
© Copyright IBM Corp. 1999, 2000
91