Datasheet, Volume 1
5
7
Electrical Specifications
...........................................................................................
61
7.1
Power and Ground Lands
....................................................................................
61
7.2
Decoupling Guidelines
........................................................................................
61
7.2.1
Voltage Rail Decoupling
...........................................................................
61
7.3
Processor Clocking (BCLK[0], BCLK#[0])
..............................................................
62
7.3.1
PLL Power Supply
...................................................................................
62
7.4
V
CC
Voltage Identification (VID)
..........................................................................
62
7.5
Reserved or Unused Signals
................................................................................
66
7.6
Signal Groups
...................................................................................................
66
7.7
Test Access Port (TAP) Connection
.......................................................................
69
7.8
Absolute Maximum and Minimum Ratings
.............................................................
69
7.9
DC Specifications
..............................................................................................
70
7.9.1
Voltage and Current Specifications
............................................................
70
7.10
Platform Environmental Control Interface (PECI) DC Specifications
...........................
77
7.10.1
DC Characteristics
..................................................................................
77
7.10.2
Input Device Hysteresis
..........................................................................
78
8
Processor Land and Signal Information
...................................................................
79
8.1
Processor Land Assignments
...............................................................................
79
Figures
1-1 Intel
®
Xeon
®
Processor 3400 Series Platform Diagram
.................................................
10
2-1 Intel
®
Flex Memory Technology Operation
...................................................................
22
2-2
Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
..................
23
2-3
PCI Express* Layering Diagram
.................................................................................
25
2-4
Packet Flow through the Layers
.................................................................................
26
2-5
PCI Express* Related Register Structures in Processor
.................................................
27
4-1
Idle Power Management Breakdown of the Processor Cores
...........................................
37
4-2
Thread and Core C-State Entry and Exit
......................................................................
38
4-3
Package C-State Entry and Exit
..................................................................................
42
7-1 V
CC
Static and Transient Tolerance Loadlines
...............................................................
73
7-2
Input Device Hysteresis
............................................................................................
78
8-1
Socket Pinmap (Top View, Upper-Left Quadrant)
..........................................................
80
8-2
Socket Pinmap (Top View, Upper-Right Quadrant)
........................................................
81
8-3
Socket Pinmap (Top View, Lower-Left Quadrant)
..........................................................
82
8-4
Socket Pinmap (Top View, Lower-Right Quadrant)
........................................................
83
Tables
1-1
Intel
®
Xeon
®
Processor 3400 Series Supported Memory Summary
................................
11
1-2
Related Documents
.................................................................................................
17
2-1
Supported DIMM Module Configurations
.....................................................................
20
2-2
DDR3 System Memory Timing Support
.....................................................................
21
2-3
System Memory Pre-Charge Power Down Support
.......................................................
24
2-4
Processor Reference Clock Requirements
...................................................................
29
4-1
Processor Core/Package State Support
......................................................................
35
4-2
G, S, and C State Combinations
................................................................................
36
4-3
Coordination of Thread Power States at the Core Level
................................................
38
4-4
P_LVLx to MWAIT Conversion
...................................................................................
39
4-5
Coordination of Core Power States at the Package Level
...............................................
41
4-6
Targeted Memory State Conditions
............................................................................
44
6-1
Signal Description Buffer Types
................................................................................
49
6-2
Memory Channel A
..................................................................................................
50
6-3
Memory Channel B
..................................................................................................
51
6-4
Memory Reference and Compensation
.......................................................................
52