Intel BX80605X3430 Data Sheet - Page 50

Signal Description 6.1 System Memory Interface Table 6-2. Memory Channel A Signal Name SA_BS[2:0] SA_CAS# SA_CK#[1:0] SA_CK#[3:2] SA_CK[1:0] SA_CK[3:2] SA_CKE[3:0] SA_CS#[3:0] SA_CS#[7:4] SA_DM[7:0] SA_DQ[63:0] SA_DQS[8:0] SA_DQS#[8:0] SA_ECC_CB[7:0] SA_MA[15:0] SA_ODT[3:0] SA_RAS# SA_WE# Description Bank Select: These signals define which banks are selected within each SDRAM rank. CAS Control Signal: This signal is used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SDRAM Commands. SDRAM Inverted Differential Clock: Channel A SDRAM Differential clock signal-pair complement. SDRAM Inverted Differential Clock: Channel A SDRAM Differential clock signal-pair complement. SDRAM Differential Clock: Channel A SDRAM Differential clock signal pair. The crossing of the positive edge of SA_CKx and the negative edge of its complement SA_CKx# are used to sample the command and control signals on the SDRAM. SDRAM Differential Clock: Channel A SDRAM Differential clock signal pair. The crossing of the positive edge of SA_CKx and the negative edge of its complement SA_CKx# are used to sample the command and control signals on the SDRAM. Clock Enable: (1 per rank). These signals are used to: • Initialize the SDRAMs during power-up • Power-down SDRAM ranks • Place all SDRAM ranks into and out of self-refresh during STR Chip Select: (1 per rank) These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank. These signals are only used for processors and platforms that have Registered DIMM support. These signals are used to select particular SDRAM components during the active state and SA_CS#[7:6] are used as the on die termination for the first DIMM. Data Mask: These signals are used to mask individual bytes of data in the case of a partial write, and to interrupt burst writes. When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SA_DM[7:0] for every data byte lane. Note: These signals are not used by the Intel Xeon processor 3400 series. They are connected to VSS on the package. Data Bus: Channel A data signal interface to the SDRAM data bus. Data Strobes: SA_DQS[8:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SA_DQS[8:0] and its SA_DQS#[8:0] during read and write transactions. Data Lines for ECC Check Byte. Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM. On Die Termination: Active Termination Control RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands. Write Enable Control Signal: This signal is used with SA_RAS# and SA_CAS# (along with SA_CS#) to define the SDRAM Commands. Direction O O O O O O O O O I/O I/O I/O O O O O Type DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 DDR3 50 Datasheet, Volume 1