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Intel BX80605X3430 Data Sheet - Page 92

Intel BX80605X3430 - Xeon 2.4 GHz Processor Manual

UPC - 735858210331

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Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC K35 K36 K38 K39 L17 L19 L20 L22 L23 L25 L26 L28 L29 L31 L32 L34 L35 L37 L38 L40 M17 M19 M21 M22 M24 M25 M27 M28 M30 M33 M34 M36 M37 M39 M40 N33 N35 N36 N38 N39 P33 P34 P35 P36 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC P37 PWR VCC P38 PWR VCC P39 PWR VCC P40 PWR VCC R33 PWR VCC R34 PWR VCC R35 PWR VCC R36 PWR VCC R37 PWR VCC R38 PWR VCC R39 PWR VCC R40 PWR VCC_NCTF A38 PWR VCC_NCTF C40 PWR VCC_SENSE T35 Analog VCCPLL AF7 PWR VCCPLL AF8 PWR VCCPLL AG8 PWR VCCPWRGOOD_0 AH35 Asynch I VCCPWRGOOD_1 AH36 Asynch I VDDQ AJ11 PWR VDDQ AJ13 PWR VDDQ AJ15 PWR VDDQ AT10 PWR VDDQ AT18 PWR VDDQ AT21 PWR VDDQ AU11 PWR VDDQ AV13 PWR VDDQ AV16 PWR VDDQ AV19 PWR VDDQ AV22 PWR VDDQ AV25 PWR VDDQ AV28 PWR VDDQ AW9 PWR VDDQ AY11 PWR VDDQ AY14 PWR VDDQ AY17 PWR VDDQ AY23 PWR VDDQ AY26 PWR VID[0]/MSID[0] U40 CMOS I/O VID[1]/MSID[1] U39 CMOS I/O VID[2]/MSID[2] U38 CMOS I/O VID[3]/CSC[0] U37 CMOS I/O VID[4]/CSC[1] U36 CMOS I/O 92 Datasheet, Volume 1

Section	Page
1 Introduction	9
1.1 Processor Feature Details	11
1.1.1 Supported Technologies	11
1.2 Interfaces	11
1.2.1 System Memory Support	11
1.2.2 PCI Express*	12
1.2.3 Direct Media Interface (DMI)	13
1.2.4 Platform Environment Control Interface (PECI)	14
1.3 Power Management Support	14
1.3.1 Processor Core	14
1.3.2 System	14
1.3.3 Memory Controller	14
1.3.4 PCI Express*	14
1.4 Thermal Management Support	15
1.5 Package	15
1.6 Terminology	15
1.7 Related Documents	17
2 Interfaces	19
2.1 System Memory Interface	19
2.1.1 System Memory Technology Supported	19
2.1.2 System Memory Timing Support	21
2.1.3 System Memory Organization Modes	21
2.1.3.1 Single-Channel Mode	21
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode	22
2.1.4 Rules for Populating Memory Slots	23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)	24
2.1.5.1 Just-in-Time Command Scheduling	24
2.1.5.2 Command Overlap	24
2.1.5.3 Out-of-Order Scheduling	24
2.1.6 System Memory Pre-Charge Power Down Support Details	24
2.2 PCI Express* Interface	25
2.2.1 PCI Express* Architecture	25
2.2.1.1 Transaction Layer	26
2.2.1.2 Data Link Layer	26
2.2.1.3 Physical Layer	26
2.2.2 PCI Express* Configuration Mechanism	27
2.2.3 PCI Express* Ports and Bifurcation	28
2.2.3.1 PCI Express* Bifurcated Mode	28
2.3 Direct Media Interface (DMI)	28
2.3.1 DMI Error Flow	28
2.3.2 Processor/PCH Compatibility Assumptions	28
2.3.3 DMI Link Down	28
2.4 Platform Environment Control Interface (PECI)	29
2.5 Interface Clocking	29
2.5.1 Internal Clocking Requirements	29
3 Technologies	31
3.1 Intel® Virtualization Technology	31
3.1.1 Intel® VT-x Objectives	31
3.1.2 Intel® VT-x Features	31
3.1.3 Intel® VT-d Objectives	32
3.1.4 Intel® VT-d Features	32
3.1.5 Intel® VT-d Features Not Supported	33
3.2 Intel® Trusted Execution Technology (Intel® TXT)	33
3.3 Intel® Hyper-Threading Technology	34
3.4 Intel® Turbo Boost Technology	34
4 Power Management	35
4.1 ACPI States Supported	35
4.1.1 System States	35
4.1.2 Processor Core/Package Idle States	35
4.1.3 Integrated Memory Controller States	35
4.1.4 PCI Express* Link States	36
4.1.5 Interface State Combinations	36
4.2 Processor Core Power Management	36
4.2.1 Enhanced Intel® SpeedStep® Technology	37
4.2.2 Low-Power Idle States	37
4.2.3 Requesting Low-Power Idle States	39
4.2.4 Core C-states	39
4.2.4.1 Core C0 State	40
4.2.4.2 Core C1/C1E State	40
4.2.4.3 Core C3 State	40
4.2.4.4 Core C6 State	40
4.2.4.5 C-State Auto-Demotion	40
4.2.5 Package C-States	41
4.2.5.1 Package C0	42
4.2.5.2 Package C1/C1E	42
4.2.5.3 Package C3 State	43
4.2.5.4 Package C6 State	43
4.3 IMC Power Management	43
4.3.1 Disabling Unused System Memory Outputs	43
4.3.2 DRAM Power Management and Initialization	44
4.3.2.1 Initialization Role of CKE	44
4.3.2.2 Conditional Self-Refresh	44
4.3.2.3 Dynamic Power Down Operation	44
4.3.2.4 DRAM I/O Power Management	45
4.4 PCI Express* Power Management	45
5 Thermal Management	47
6 Signal Description	49
6.1 System Memory Interface	50
6.2 Memory Reference and Compensation	52
6.3 Reset and Miscellaneous Signals	52
6.4 PCI Express* Based Interface Signals	53
6.5 DMI—Processor to PCH Serial Interface	53
6.6 PLL Signals	54
6.7 Intel® Flexible Display Interface Signals	54
6.8 JTAG/ITP Signals	55
6.9 Error and Thermal Protection	56
6.10 Power Sequencing	57
6.11 Processor Core Power Signals	57
6.12 Graphics and Memory Core Power Signals	59
6.13 Ground and NCTF	60
6.14 Processor Internal Pull Up/Pull Down	60
7 Electrical Specifications	61
7.1 Power and Ground Lands	61
7.2 Decoupling Guidelines	61
7.2.1 Voltage Rail Decoupling	61
7.3 Processor Clocking (BCLK[0], BCLK#[0])	62
7.3.1 PLL Power Supply	62
7.4 VCC Voltage Identification (VID)	62
7.5 Reserved or Unused Signals	66
7.6 Signal Groups	66
7.7 Test Access Port (TAP) Connection	69
7.8 Absolute Maximum and Minimum Ratings	69
7.9 DC Specifications	70
7.9.1 Voltage and Current Specifications	70
7.10 Platform Environmental Control Interface (PECI) DC Specifications	77
7.10.1 DC Characteristics	77
7.10.2 Input Device Hysteresis	78
8 Processor Land and Signal Information	79

Match case Limit results 1 per page

Datasheet, Volume 1

Processor Land and Signal Information

VCC

K35

PWR

VCC

K36

PWR

VCC

K38

PWR

VCC

K39

PWR

VCC

L17

PWR

VCC

L19

PWR

VCC

L20

PWR

VCC

L22

PWR

VCC

L23

PWR

VCC

L25

PWR

VCC

L26

PWR

VCC

L28

PWR

VCC

L29

PWR

VCC

L31

PWR

VCC

L32

PWR

VCC

L34

PWR

VCC

L35

PWR

VCC

L37

PWR

VCC

L38

PWR

VCC

L40

PWR

VCC

M17

PWR

VCC

M19

PWR

VCC

M21

PWR

VCC

M22

PWR

VCC

M24

PWR

VCC

M25

PWR

VCC

M27

PWR

VCC

M28

PWR

VCC

M30

PWR

VCC

M33

PWR

VCC

M34

PWR

VCC

M36

PWR

VCC

M37

PWR

VCC

M39

PWR

VCC

M40

PWR

VCC

N33

PWR

VCC

N35

PWR

VCC

N36

PWR

VCC

N38

PWR

VCC

N39

PWR

VCC

P33

PWR

VCC

P34

PWR

VCC

P35

PWR

VCC

P36

PWR

Table 8-2.

Processor Pin List by Pin

Name

Pin Name

Pin #

Buffer Type

Dir.

VCC

P37

PWR

VCC

P38

PWR

VCC

P39

PWR

VCC

P40

PWR

VCC

R33

PWR

VCC

R34

PWR

VCC

R35

PWR

VCC

R36

PWR

VCC

R37

PWR

VCC

R38

PWR

VCC

R39

PWR

VCC

R40

PWR

VCC_NCTF

A38

PWR

VCC_NCTF

C40

PWR

VCC_SENSE

T35

Analog

VCCPLL

AF7

PWR

VCCPLL

AF8

PWR

VCCPLL

AG8

PWR

VCCPWRGOOD_0

AH35

Asynch

VCCPWRGOOD_1

AH36

Asynch

VDDQ

AJ11

PWR

VDDQ

AJ13

PWR

VDDQ

AJ15

PWR

VDDQ

AT10

PWR

VDDQ

AT18

PWR

VDDQ

AT21

PWR

VDDQ

AU11

PWR

VDDQ

AV13

PWR

VDDQ

AV16

PWR

VDDQ

AV19

PWR

VDDQ

AV22

PWR

VDDQ

AV25

PWR

VDDQ

AV28

PWR

VDDQ

AW9

PWR

VDDQ

AY11

PWR

VDDQ

AY14

PWR

VDDQ

AY17

PWR

VDDQ

AY23

PWR

VDDQ

AY26

PWR

VID[0]/MSID[0]

U40

CMOS

I/O

VID[1]/MSID[1]

U39

CMOS

I/O

VID[2]/MSID[2]

U38

CMOS

I/O

VID[3]/CSC[0]

U37

CMOS

I/O

VID[4]/CSC[1]

U36

CMOS

I/O

Table 8-2.

Processor Pin List by Pin

Name

Pin Name

Pin #

Buffer Type

Dir.