Home » Intel Manuals » Processors » Intel BX80605X3430 » Manual Viewer

Intel BX80605X3430 Data Sheet - Page 58

Table 6-13., Processor Core Power Signals Sheet 2 of 2

UPC - 735858210331

Add to My Manuals
Save this manual to your list of manuals

Page 58 highlights

Signal Description Table 6-13. Processor Core Power Signals (Sheet 2 of 2) Signal Name VID[7:6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] VSS_SENSE VSS_SENSE_VTT VTT VTT_SELECT VTT_SENSE Description VID[7:0] (Voltage ID) are used to support automatic sVeolletacgtieonReogf uploawtoerr-Dsuopwpnly(VvRolDta)g1e1s.1(VDCeC)s.igRneGfeuridtoeltinhees for more information. The voltage supply for these signals must be valid before the VR can supply the processor. Conversely, the VR output must bVeCC to disabled until the voltage supply for the VID signals become valid. The VR must supply the voltage that is requested by the signals, or disable itself. VID7 1 k raensdistVoIrD(6ThshisovualdlubeeistieladtcsheepdaroantetlhyetorisVinSSg using edge a of VTTPWRGOOD). CSC[2:0]-Current Sense Configuration bits, for ISENSE gain setting. See Voltage Regulator-Down (VRD) 11.1 Design Guidelines for gain setting information. This value is latched on the rising edge of VTTPWRGOOD. MSID[2:0] (Market Segment Identification) are used to indicate the maximum platform capability to the processor. A processor will only boot if the MSID[2:0] pins are strapped to the appropriate setting (or higher) on the platform (see Table 7-3 for MSID encodings). MSID is used to help protect the platform by preventing a higher power processor from booting in a platform designed for lower power processors. MSID[2:0] are latched on the rising edge of VTTPWRGOOD. VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to the processor core voltage and ground. They can be used to sense or measure voltage near the silicon. VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance connection to the processor VTT voltage and ground. They can be used to sense or measure voltage near the silicon. Processor power for the memory controller, shared cache and I/O (1.1 V). The VTT_SELECT signal is used to select the correct VTT voltage level for the processor. The processor will be configured to drive a low voltage level for VTT_SELECT. VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance connection to the processor VTT voltage and ground. They can be used to sense or measure voltage near the silicon. Direction I/O O Type CMOS Analog Analog PWR CMOS Analog 58 Datasheet, Volume 1

Section	Page
1 Introduction	9
1.1 Processor Feature Details	11
1.1.1 Supported Technologies	11
1.2 Interfaces	11
1.2.1 System Memory Support	11
1.2.2 PCI Express*	12
1.2.3 Direct Media Interface (DMI)	13
1.2.4 Platform Environment Control Interface (PECI)	14
1.3 Power Management Support	14
1.3.1 Processor Core	14
1.3.2 System	14
1.3.3 Memory Controller	14
1.3.4 PCI Express*	14
1.4 Thermal Management Support	15
1.5 Package	15
1.6 Terminology	15
1.7 Related Documents	17
2 Interfaces	19
2.1 System Memory Interface	19
2.1.1 System Memory Technology Supported	19
2.1.2 System Memory Timing Support	21
2.1.3 System Memory Organization Modes	21
2.1.3.1 Single-Channel Mode	21
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode	22
2.1.4 Rules for Populating Memory Slots	23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)	24
2.1.5.1 Just-in-Time Command Scheduling	24
2.1.5.2 Command Overlap	24
2.1.5.3 Out-of-Order Scheduling	24
2.1.6 System Memory Pre-Charge Power Down Support Details	24
2.2 PCI Express* Interface	25
2.2.1 PCI Express* Architecture	25
2.2.1.1 Transaction Layer	26
2.2.1.2 Data Link Layer	26
2.2.1.3 Physical Layer	26
2.2.2 PCI Express* Configuration Mechanism	27
2.2.3 PCI Express* Ports and Bifurcation	28
2.2.3.1 PCI Express* Bifurcated Mode	28
2.3 Direct Media Interface (DMI)	28
2.3.1 DMI Error Flow	28
2.3.2 Processor/PCH Compatibility Assumptions	28
2.3.3 DMI Link Down	28
2.4 Platform Environment Control Interface (PECI)	29
2.5 Interface Clocking	29
2.5.1 Internal Clocking Requirements	29
3 Technologies	31
3.1 Intel® Virtualization Technology	31
3.1.1 Intel® VT-x Objectives	31
3.1.2 Intel® VT-x Features	31
3.1.3 Intel® VT-d Objectives	32
3.1.4 Intel® VT-d Features	32
3.1.5 Intel® VT-d Features Not Supported	33
3.2 Intel® Trusted Execution Technology (Intel® TXT)	33
3.3 Intel® Hyper-Threading Technology	34
3.4 Intel® Turbo Boost Technology	34
4 Power Management	35
4.1 ACPI States Supported	35
4.1.1 System States	35
4.1.2 Processor Core/Package Idle States	35
4.1.3 Integrated Memory Controller States	35
4.1.4 PCI Express* Link States	36
4.1.5 Interface State Combinations	36
4.2 Processor Core Power Management	36
4.2.1 Enhanced Intel® SpeedStep® Technology	37
4.2.2 Low-Power Idle States	37
4.2.3 Requesting Low-Power Idle States	39
4.2.4 Core C-states	39
4.2.4.1 Core C0 State	40
4.2.4.2 Core C1/C1E State	40
4.2.4.3 Core C3 State	40
4.2.4.4 Core C6 State	40
4.2.4.5 C-State Auto-Demotion	40
4.2.5 Package C-States	41
4.2.5.1 Package C0	42
4.2.5.2 Package C1/C1E	42
4.2.5.3 Package C3 State	43
4.2.5.4 Package C6 State	43
4.3 IMC Power Management	43
4.3.1 Disabling Unused System Memory Outputs	43
4.3.2 DRAM Power Management and Initialization	44
4.3.2.1 Initialization Role of CKE	44
4.3.2.2 Conditional Self-Refresh	44
4.3.2.3 Dynamic Power Down Operation	44
4.3.2.4 DRAM I/O Power Management	45
4.4 PCI Express* Power Management	45
5 Thermal Management	47
6 Signal Description	49
6.1 System Memory Interface	50
6.2 Memory Reference and Compensation	52
6.3 Reset and Miscellaneous Signals	52
6.4 PCI Express* Based Interface Signals	53
6.5 DMI—Processor to PCH Serial Interface	53
6.6 PLL Signals	54
6.7 Intel® Flexible Display Interface Signals	54
6.8 JTAG/ITP Signals	55
6.9 Error and Thermal Protection	56
6.10 Power Sequencing	57
6.11 Processor Core Power Signals	57
6.12 Graphics and Memory Core Power Signals	59
6.13 Ground and NCTF	60
6.14 Processor Internal Pull Up/Pull Down	60
7 Electrical Specifications	61
7.1 Power and Ground Lands	61
7.2 Decoupling Guidelines	61
7.2.1 Voltage Rail Decoupling	61
7.3 Processor Clocking (BCLK[0], BCLK#[0])	62
7.3.1 PLL Power Supply	62
7.4 VCC Voltage Identification (VID)	62
7.5 Reserved or Unused Signals	66
7.6 Signal Groups	66
7.7 Test Access Port (TAP) Connection	69
7.8 Absolute Maximum and Minimum Ratings	69
7.9 DC Specifications	70
7.9.1 Voltage and Current Specifications	70
7.10 Platform Environmental Control Interface (PECI) DC Specifications	77
7.10.1 DC Characteristics	77
7.10.2 Input Device Hysteresis	78
8 Processor Land and Signal Information	79

Match case Limit results 1 per page

Signal Description

Datasheet, Volume 1

VID[7:6]

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

VID[7:0] (Voltage ID) are used to support automatic

selection of power supply voltages (V

). Refer to the

Voltage Regulator-Down (VRD) 11.1 Design Guidelines

for more information. The voltage supply for these

signals must be valid before the VR can supply V

the processor. Conversely, the VR output must be

disabled until the voltage supply for the VID signals

become valid. The VR must supply the voltage that is

requested by the signals, or disable itself.

VID7 and VID6 should be tied separately to V

using a



resistor (This value is latched on the rising edge of

VTTPWRGOOD).

CSC[2:0]—Current Sense Configuration bits, for ISENSE

gain setting. See Voltage Regulator-Down (VRD) 11.1

Design Guidelines for gain setting information. This

value is latched on the rising edge of VTTPWRGOOD.

MSID[2:0] (Market Segment Identification) are used to

indicate the maximum platform capability to the

processor. A processor will only boot if the MSID[2:0]

pins are strapped to the appropriate setting (or higher)

on the platform (see

Table 7-3

for MSID encodings).

MSID is used to help protect the platform by preventing

a higher power processor from booting in a platform

designed for lower power processors. MSID[2:0] are

latched on the rising edge of VTTPWRGOOD.

I/O

CMOS

VSS_SENSE

VCC_SENSE and VSS_SENSE provide an isolated, low

impedance connection to the processor core voltage

and ground. They can be used to sense or measure

voltage near the silicon.

Analog

VSS_SENSE_VTT

VTT_SENSE and VSS_SENSE_VTT provide an isolated,

low impedance connection to the processor V

voltage

and ground. They can be used to sense or measure

voltage near the silicon.

Analog

VTT

Processor power for the memory controller, shared cache

and I/O (1.1 V).

PWR

VTT_SELECT

The VTT_SELECT signal is used to select the correct V

voltage level for the processor. The processor will be

configured to drive a low voltage level for VTT_SELECT.

CMOS

VTT_SENSE

VTT_SENSE and VSS_SENSE_VTT provide an isolated,

low impedance connection to the processor V

voltage

and ground. They can be used to sense or measure

voltage near the silicon.

Analog

Table 6-13.

Processor Core Power Signals (Sheet 2 of 2)

Signal Name

Description

Direction

Type