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Intel BX80605X3430 Data Sheet - Page 68

Table 7-3., Signal Groups Sheet 2 of 2

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Electrical Specifications Table 7-3. Signal Groups (Sheet 2 of 2)1 Signal Group Single Ended Single Ended Alpha Group (qb) (r) Single Ended (s) Single Ended Single Ended Power/Ground/Other Single Ended PCI Express* Differential Differential Single Ended DMI Differential Differential Intel® FDI Single Ended Differential (t) (ta) (u) (v) (w) (x) (y) (z) (ac) (ad) (ae) (af) (ag) (ah) (ai) Type CMOS Input CMOS Output CMOS Bi-directional Analog Input Analog Output Signals RSTIN# VTT_SELECT VID[7:6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] COMP0, COMP1, COMP2, COMP3, SM_RCOMP[2:0], ISENSE SA_DIMM_VREFDQ SB_DIMM_VREFDQ Power Ground No Connect Asynchronous CMOS Output Sense Points Other VCC, VCC_NCTF, VTT, VCCPLL, VDDQ, VAXG VSS, CGC_TP_NCTF RSVD, RSVD_NCTF, RSVD_TP, FC_x PSI# VCC_SENSE, VSS_SENSE, VTT_SENSE, VSS_SENSE_VTT, VAXG_SENSE, VSSAXG_SENSE SKTOCC#, DBR# PCI Express Input PCI Express Output Analog Input PEG_RX[15:0], PEG_RX#[15:0] PEG_TX[15:0], PEG_TX#[15:0] PEG_ICOMP0, PEG_ICOMPI, PEG_RCOMP0, PEG_RBIAS DMI Input DMI Output FDI Input FDI Output DMI_RX[3:0], DMI_RX#[3:0] DMI_TX[3:0], DMI_TX#[3:0] FDI_FSYNC[1:0]4, FDI_LSYNC[1:0]4, FDI_INT4 FDI_TX[7:0]4, FDI_TX#[7:0]4 Notes: 1. Refer to Chapter 6 for signal description details. 2. SA and SB refer to DDR3 Channel A and DDR3 Channel B. 3. These signals are only used on processors and platforms that support ECC DIMMs. 4. These signals will not be actively used on the Intel Xeon processor 3400 series. All Control Sideband Asynchronous signals are required to be asserted/de-asserted for at least eight BCLKs for the processor to recognize the proper signal state. See Section 7.9 for the DC specifications. 68 Datasheet, Volume 1

Section	Page
1 Introduction	9
1.1 Processor Feature Details	11
1.1.1 Supported Technologies	11
1.2 Interfaces	11
1.2.1 System Memory Support	11
1.2.2 PCI Express*	12
1.2.3 Direct Media Interface (DMI)	13
1.2.4 Platform Environment Control Interface (PECI)	14
1.3 Power Management Support	14
1.3.1 Processor Core	14
1.3.2 System	14
1.3.3 Memory Controller	14
1.3.4 PCI Express*	14
1.4 Thermal Management Support	15
1.5 Package	15
1.6 Terminology	15
1.7 Related Documents	17
2 Interfaces	19
2.1 System Memory Interface	19
2.1.1 System Memory Technology Supported	19
2.1.2 System Memory Timing Support	21
2.1.3 System Memory Organization Modes	21
2.1.3.1 Single-Channel Mode	21
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode	22
2.1.4 Rules for Populating Memory Slots	23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)	24
2.1.5.1 Just-in-Time Command Scheduling	24
2.1.5.2 Command Overlap	24
2.1.5.3 Out-of-Order Scheduling	24
2.1.6 System Memory Pre-Charge Power Down Support Details	24
2.2 PCI Express* Interface	25
2.2.1 PCI Express* Architecture	25
2.2.1.1 Transaction Layer	26
2.2.1.2 Data Link Layer	26
2.2.1.3 Physical Layer	26
2.2.2 PCI Express* Configuration Mechanism	27
2.2.3 PCI Express* Ports and Bifurcation	28
2.2.3.1 PCI Express* Bifurcated Mode	28
2.3 Direct Media Interface (DMI)	28
2.3.1 DMI Error Flow	28
2.3.2 Processor/PCH Compatibility Assumptions	28
2.3.3 DMI Link Down	28
2.4 Platform Environment Control Interface (PECI)	29
2.5 Interface Clocking	29
2.5.1 Internal Clocking Requirements	29
3 Technologies	31
3.1 Intel® Virtualization Technology	31
3.1.1 Intel® VT-x Objectives	31
3.1.2 Intel® VT-x Features	31
3.1.3 Intel® VT-d Objectives	32
3.1.4 Intel® VT-d Features	32
3.1.5 Intel® VT-d Features Not Supported	33
3.2 Intel® Trusted Execution Technology (Intel® TXT)	33
3.3 Intel® Hyper-Threading Technology	34
3.4 Intel® Turbo Boost Technology	34
4 Power Management	35
4.1 ACPI States Supported	35
4.1.1 System States	35
4.1.2 Processor Core/Package Idle States	35
4.1.3 Integrated Memory Controller States	35
4.1.4 PCI Express* Link States	36
4.1.5 Interface State Combinations	36
4.2 Processor Core Power Management	36
4.2.1 Enhanced Intel® SpeedStep® Technology	37
4.2.2 Low-Power Idle States	37
4.2.3 Requesting Low-Power Idle States	39
4.2.4 Core C-states	39
4.2.4.1 Core C0 State	40
4.2.4.2 Core C1/C1E State	40
4.2.4.3 Core C3 State	40
4.2.4.4 Core C6 State	40
4.2.4.5 C-State Auto-Demotion	40
4.2.5 Package C-States	41
4.2.5.1 Package C0	42
4.2.5.2 Package C1/C1E	42
4.2.5.3 Package C3 State	43
4.2.5.4 Package C6 State	43
4.3 IMC Power Management	43
4.3.1 Disabling Unused System Memory Outputs	43
4.3.2 DRAM Power Management and Initialization	44
4.3.2.1 Initialization Role of CKE	44
4.3.2.2 Conditional Self-Refresh	44
4.3.2.3 Dynamic Power Down Operation	44
4.3.2.4 DRAM I/O Power Management	45
4.4 PCI Express* Power Management	45
5 Thermal Management	47
6 Signal Description	49
6.1 System Memory Interface	50
6.2 Memory Reference and Compensation	52
6.3 Reset and Miscellaneous Signals	52
6.4 PCI Express* Based Interface Signals	53
6.5 DMI—Processor to PCH Serial Interface	53
6.6 PLL Signals	54
6.7 Intel® Flexible Display Interface Signals	54
6.8 JTAG/ITP Signals	55
6.9 Error and Thermal Protection	56
6.10 Power Sequencing	57
6.11 Processor Core Power Signals	57
6.12 Graphics and Memory Core Power Signals	59
6.13 Ground and NCTF	60
6.14 Processor Internal Pull Up/Pull Down	60
7 Electrical Specifications	61
7.1 Power and Ground Lands	61
7.2 Decoupling Guidelines	61
7.2.1 Voltage Rail Decoupling	61
7.3 Processor Clocking (BCLK[0], BCLK#[0])	62
7.3.1 PLL Power Supply	62
7.4 VCC Voltage Identification (VID)	62
7.5 Reserved or Unused Signals	66
7.6 Signal Groups	66
7.7 Test Access Port (TAP) Connection	69
7.8 Absolute Maximum and Minimum Ratings	69
7.9 DC Specifications	70
7.9.1 Voltage and Current Specifications	70
7.10 Platform Environmental Control Interface (PECI) DC Specifications	77
7.10.1 DC Characteristics	77
7.10.2 Input Device Hysteresis	78
8 Processor Land and Signal Information	79

Match case Limit results 1 per page

Electrical Specifications

Datasheet, Volume 1

Notes:

Refer to

Chapter 6

for signal description details.

SA and SB refer to DDR3 Channel A and DDR3 Channel B.

These signals are only used on processors and platforms that support ECC DIMMs.

These signals will not be actively used on the Intel Xeon processor 3400 series.

All Control Sideband Asynchronous signals are required to be asserted/de-asserted for

at least eight BCLKs for the processor to recognize the proper signal state. See

Section 7.9

for the DC specifications.

Single Ended

(qb)

CMOS Input

RSTIN#

Single Ended

(r)

CMOS Output

VTT_SELECT

Single Ended

(s)

CMOS Bi-directional

VID[7:6]

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

Single Ended

(t)

Analog Input

COMP0, COMP1, COMP2, COMP3,

SM_RCOMP[2:0], ISENSE

Single Ended

(ta)

Analog Output

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

Power/Ground/Other

(u)

Power

VCC, VCC_NCTF, VTT, VCCPLL,

VDDQ, VAXG

(v)

Ground

VSS, CGC_TP_NCTF

(w)

No Connect

RSVD, RSVD_NCTF, RSVD_TP,

FC_x

Single Ended

(x)

Asynchronous CMOS

Output

PSI#

(y)

Sense Points

VCC_SENSE, VSS_SENSE,

VTT_SENSE, VSS_SENSE_VTT,

VAXG_SENSE, VSSAXG_SENSE

(z)

Other

SKTOCC#, DBR#

PCI Express*

Differential

(ac)

PCI Express Input

PEG_RX[15:0], PEG_RX#[15:0]

Differential

(ad)

PCI Express Output

PEG_TX[15:0], PEG_TX#[15:0]

Single Ended

(ae)

Analog Input

PEG_ICOMP0, PEG_ICOMPI,

PEG_RCOMP0, PEG_RBIAS

DMI

Differential

(af)

DMI Input

DMI_RX[3:0], DMI_RX#[3:0]

Differential

(ag)

DMI Output

DMI_TX[3:0], DMI_TX#[3:0]

Intel

FDI

Single Ended

(ah)

FDI Input

FDI_FSYNC[1:0]

FDI_LSYNC[1:0]

, FDI_INT

Differential

(ai)

FDI Output

FDI_TX[7:0]

, FDI_TX#[7:0]

Table 7-3.

Signal Groups (Sheet 2 of 2)

Signal Group

Alpha

Group

Type

Signals