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Intel BX80605X3430 Data Sheet - Page 77

Platform Environmental Control Interface PECI, DC Specifications

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Electrical Specifications 7.10 Platform Environmental Control Interface (PECI) DC Specifications PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. For the PECI command set supported by the processor, refer to the appropriate processor Thermal and Mechanical Specifications and Design Guidelines for additional information (see Section 1.7). 7.10.1 DC Characteristics The PECI interface operates at a nominal voltage set by VTT. The set of DC electrical specifications shown in Table 7-11 is used with devices normally operating from a VTT interface supply. VTT nominal levels will vary between processor families. All PECI devices will operate at the VTT level determined by the processor installed in the system. For specific nominal VTT levels, refer to Table 7-6. Table 7-11. PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range -0.150 VTT V Vhysteresis Hysteresis 0.1 * VTT N/A V Vn Negative-Edge Threshold Voltage 0.275 * VTT 0.500 * VTT V Vp Positive-Edge Threshold Voltage 0.550 * VTT 0.725 * VTT V Isource High-Level Output Source (VOH = 0.75 * VTT) -6.0 N/A mA Isink Low-Level Output Sink (VOL = 0.25 * VTT) 0.5 1.0 mA Ileak+ High Impedance State Leakage to VTT (Vleak = VOL) N/A 100 µA 2 Ileak- High Impedance Leakage to GND (Vleak = VOH) N/A 100 µA 2 Cbus Bus Capacitance per Node N/A 10 pF Vnoise Signal Noise Immunity above 300 MHz 0.1 * VTT N/A Vp-p Notes: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus. Datasheet, Volume 1 77

Section	Page
1 Introduction	9
1.1 Processor Feature Details	11
1.1.1 Supported Technologies	11
1.2 Interfaces	11
1.2.1 System Memory Support	11
1.2.2 PCI Express*	12
1.2.3 Direct Media Interface (DMI)	13
1.2.4 Platform Environment Control Interface (PECI)	14
1.3 Power Management Support	14
1.3.1 Processor Core	14
1.3.2 System	14
1.3.3 Memory Controller	14
1.3.4 PCI Express*	14
1.4 Thermal Management Support	15
1.5 Package	15
1.6 Terminology	15
1.7 Related Documents	17
2 Interfaces	19
2.1 System Memory Interface	19
2.1.1 System Memory Technology Supported	19
2.1.2 System Memory Timing Support	21
2.1.3 System Memory Organization Modes	21
2.1.3.1 Single-Channel Mode	21
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode	22
2.1.4 Rules for Populating Memory Slots	23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)	24
2.1.5.1 Just-in-Time Command Scheduling	24
2.1.5.2 Command Overlap	24
2.1.5.3 Out-of-Order Scheduling	24
2.1.6 System Memory Pre-Charge Power Down Support Details	24
2.2 PCI Express* Interface	25
2.2.1 PCI Express* Architecture	25
2.2.1.1 Transaction Layer	26
2.2.1.2 Data Link Layer	26
2.2.1.3 Physical Layer	26
2.2.2 PCI Express* Configuration Mechanism	27
2.2.3 PCI Express* Ports and Bifurcation	28
2.2.3.1 PCI Express* Bifurcated Mode	28
2.3 Direct Media Interface (DMI)	28
2.3.1 DMI Error Flow	28
2.3.2 Processor/PCH Compatibility Assumptions	28
2.3.3 DMI Link Down	28
2.4 Platform Environment Control Interface (PECI)	29
2.5 Interface Clocking	29
2.5.1 Internal Clocking Requirements	29
3 Technologies	31
3.1 Intel® Virtualization Technology	31
3.1.1 Intel® VT-x Objectives	31
3.1.2 Intel® VT-x Features	31
3.1.3 Intel® VT-d Objectives	32
3.1.4 Intel® VT-d Features	32
3.1.5 Intel® VT-d Features Not Supported	33
3.2 Intel® Trusted Execution Technology (Intel® TXT)	33
3.3 Intel® Hyper-Threading Technology	34
3.4 Intel® Turbo Boost Technology	34
4 Power Management	35
4.1 ACPI States Supported	35
4.1.1 System States	35
4.1.2 Processor Core/Package Idle States	35
4.1.3 Integrated Memory Controller States	35
4.1.4 PCI Express* Link States	36
4.1.5 Interface State Combinations	36
4.2 Processor Core Power Management	36
4.2.1 Enhanced Intel® SpeedStep® Technology	37
4.2.2 Low-Power Idle States	37
4.2.3 Requesting Low-Power Idle States	39
4.2.4 Core C-states	39
4.2.4.1 Core C0 State	40
4.2.4.2 Core C1/C1E State	40
4.2.4.3 Core C3 State	40
4.2.4.4 Core C6 State	40
4.2.4.5 C-State Auto-Demotion	40
4.2.5 Package C-States	41
4.2.5.1 Package C0	42
4.2.5.2 Package C1/C1E	42
4.2.5.3 Package C3 State	43
4.2.5.4 Package C6 State	43
4.3 IMC Power Management	43
4.3.1 Disabling Unused System Memory Outputs	43
4.3.2 DRAM Power Management and Initialization	44
4.3.2.1 Initialization Role of CKE	44
4.3.2.2 Conditional Self-Refresh	44
4.3.2.3 Dynamic Power Down Operation	44
4.3.2.4 DRAM I/O Power Management	45
4.4 PCI Express* Power Management	45
5 Thermal Management	47
6 Signal Description	49
6.1 System Memory Interface	50
6.2 Memory Reference and Compensation	52
6.3 Reset and Miscellaneous Signals	52
6.4 PCI Express* Based Interface Signals	53
6.5 DMI—Processor to PCH Serial Interface	53
6.6 PLL Signals	54
6.7 Intel® Flexible Display Interface Signals	54
6.8 JTAG/ITP Signals	55
6.9 Error and Thermal Protection	56
6.10 Power Sequencing	57
6.11 Processor Core Power Signals	57
6.12 Graphics and Memory Core Power Signals	59
6.13 Ground and NCTF	60
6.14 Processor Internal Pull Up/Pull Down	60
7 Electrical Specifications	61
7.1 Power and Ground Lands	61
7.2 Decoupling Guidelines	61
7.2.1 Voltage Rail Decoupling	61
7.3 Processor Clocking (BCLK[0], BCLK#[0])	62
7.3.1 PLL Power Supply	62
7.4 VCC Voltage Identification (VID)	62
7.5 Reserved or Unused Signals	66
7.6 Signal Groups	66
7.7 Test Access Port (TAP) Connection	69
7.8 Absolute Maximum and Minimum Ratings	69
7.9 DC Specifications	70
7.9.1 Voltage and Current Specifications	70
7.10 Platform Environmental Control Interface (PECI) DC Specifications	77
7.10.1 DC Characteristics	77
7.10.2 Input Device Hysteresis	78
8 Processor Land and Signal Information	79

Match case Limit results 1 per page

Datasheet, Volume 1

Electrical Specifications

7.10

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between

Intel processors and chipset components to external thermal monitoring devices. The

processor contains a Digital Thermal Sensor (DTS) that reports a relative die

temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

Temperature sensors located throughout the die are implemented as analog-to-digital

converters calibrated at the factory. PECI provides an interface for external devices to

read the DTS temperature for thermal management and fan speed control. For the

PECI command set supported by the processor, refer to the appropriate processor

Thermal and Mechanical Specifications and Design Guidelines for additional information

(see

Section 1.7

7.10.1

DC Characteristics

The PECI interface operates at a nominal voltage set by V

. The set of DC electrical

specifications shown in

Table 7-11

is used with devices normally operating from a V

interface supply. V

nominal levels will vary between processor families. All PECI

devices will operate at the V

level determined by the processor installed in the

system. For specific nominal V

levels, refer to

Table 7-6

Notes:

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

The leakage specification applies to powered devices on the PECI bus.

Table 7-11.

PECI DC Electrical Limits

Symbol

Definition and Conditions

Min

Max

Units

Notes

Input Voltage Range

-0.150

hysteresis

Hysteresis

0.1 * V

N/A

Negative-Edge Threshold Voltage

0.275 * V

0.500 * V

Positive-Edge Threshold Voltage

0.550 * V

0.725 * V

source

High-Level Output Source

= 0.75 * V

)

-6.0

N/A

sink

Low-Level Output Sink

= 0.25 * V

)

0.5

1.0

leak+

High Impedance State Leakage to

leak

= V

)

N/A

100

μA

leak-

High Impedance Leakage to GND

leak

= V

)

N/A

100

μA

bus

Bus Capacitance per Node

N/A

noise

Signal Noise Immunity above

300 MHz

0.1 * V

N/A

p-p