Home » Intel Manuals » Processors » Intel BX80605X3430 » Manual Viewer

Intel BX80605X3430 Data Sheet - Page 91

Intel BX80605X3430 - Xeon 2.4 GHz Processor Manual

UPC - 735858210331

Add to My Manuals
Save this manual to your list of manuals

Page 91 highlights

Processor Land and Signal Information Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC D35 D36 D38 D39 E22 E23 E25 E26 E28 E29 E31 E32 E34 E35 E37 E38 E40 F21 F22 F24 F25 F27 F28 F30 F31 F33 F34 F36 F37 F39 F40 G20 G21 G23 G24 G26 G27 G29 G30 G32 G33 G35 G36 G38 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Table 8-2. Processor Pin List by Pin Name Pin Name Pin # Buffer Type Dir. VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC G39 H19 H20 H22 H23 H25 H26 H28 H29 H31 H32 H34 H35 H37 H38 H40 J18 J19 J21 J22 J24 J25 J27 J28 J30 J31 J33 J34 J36 J37 J39 J40 K17 K18 K20 K21 K23 K24 K26 K27 K29 K30 K32 K33 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Datasheet, Volume 1 91

Section	Page
1 Introduction	9
1.1 Processor Feature Details	11
1.1.1 Supported Technologies	11
1.2 Interfaces	11
1.2.1 System Memory Support	11
1.2.2 PCI Express*	12
1.2.3 Direct Media Interface (DMI)	13
1.2.4 Platform Environment Control Interface (PECI)	14
1.3 Power Management Support	14
1.3.1 Processor Core	14
1.3.2 System	14
1.3.3 Memory Controller	14
1.3.4 PCI Express*	14
1.4 Thermal Management Support	15
1.5 Package	15
1.6 Terminology	15
1.7 Related Documents	17
2 Interfaces	19
2.1 System Memory Interface	19
2.1.1 System Memory Technology Supported	19
2.1.2 System Memory Timing Support	21
2.1.3 System Memory Organization Modes	21
2.1.3.1 Single-Channel Mode	21
2.1.3.2 Dual-Channel Mode—Intel® Flex Memory Technology Mode	22
2.1.4 Rules for Populating Memory Slots	23
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)	24
2.1.5.1 Just-in-Time Command Scheduling	24
2.1.5.2 Command Overlap	24
2.1.5.3 Out-of-Order Scheduling	24
2.1.6 System Memory Pre-Charge Power Down Support Details	24
2.2 PCI Express* Interface	25
2.2.1 PCI Express* Architecture	25
2.2.1.1 Transaction Layer	26
2.2.1.2 Data Link Layer	26
2.2.1.3 Physical Layer	26
2.2.2 PCI Express* Configuration Mechanism	27
2.2.3 PCI Express* Ports and Bifurcation	28
2.2.3.1 PCI Express* Bifurcated Mode	28
2.3 Direct Media Interface (DMI)	28
2.3.1 DMI Error Flow	28
2.3.2 Processor/PCH Compatibility Assumptions	28
2.3.3 DMI Link Down	28
2.4 Platform Environment Control Interface (PECI)	29
2.5 Interface Clocking	29
2.5.1 Internal Clocking Requirements	29
3 Technologies	31
3.1 Intel® Virtualization Technology	31
3.1.1 Intel® VT-x Objectives	31
3.1.2 Intel® VT-x Features	31
3.1.3 Intel® VT-d Objectives	32
3.1.4 Intel® VT-d Features	32
3.1.5 Intel® VT-d Features Not Supported	33
3.2 Intel® Trusted Execution Technology (Intel® TXT)	33
3.3 Intel® Hyper-Threading Technology	34
3.4 Intel® Turbo Boost Technology	34
4 Power Management	35
4.1 ACPI States Supported	35
4.1.1 System States	35
4.1.2 Processor Core/Package Idle States	35
4.1.3 Integrated Memory Controller States	35
4.1.4 PCI Express* Link States	36
4.1.5 Interface State Combinations	36
4.2 Processor Core Power Management	36
4.2.1 Enhanced Intel® SpeedStep® Technology	37
4.2.2 Low-Power Idle States	37
4.2.3 Requesting Low-Power Idle States	39
4.2.4 Core C-states	39
4.2.4.1 Core C0 State	40
4.2.4.2 Core C1/C1E State	40
4.2.4.3 Core C3 State	40
4.2.4.4 Core C6 State	40
4.2.4.5 C-State Auto-Demotion	40
4.2.5 Package C-States	41
4.2.5.1 Package C0	42
4.2.5.2 Package C1/C1E	42
4.2.5.3 Package C3 State	43
4.2.5.4 Package C6 State	43
4.3 IMC Power Management	43
4.3.1 Disabling Unused System Memory Outputs	43
4.3.2 DRAM Power Management and Initialization	44
4.3.2.1 Initialization Role of CKE	44
4.3.2.2 Conditional Self-Refresh	44
4.3.2.3 Dynamic Power Down Operation	44
4.3.2.4 DRAM I/O Power Management	45
4.4 PCI Express* Power Management	45
5 Thermal Management	47
6 Signal Description	49
6.1 System Memory Interface	50
6.2 Memory Reference and Compensation	52
6.3 Reset and Miscellaneous Signals	52
6.4 PCI Express* Based Interface Signals	53
6.5 DMI—Processor to PCH Serial Interface	53
6.6 PLL Signals	54
6.7 Intel® Flexible Display Interface Signals	54
6.8 JTAG/ITP Signals	55
6.9 Error and Thermal Protection	56
6.10 Power Sequencing	57
6.11 Processor Core Power Signals	57
6.12 Graphics and Memory Core Power Signals	59
6.13 Ground and NCTF	60
6.14 Processor Internal Pull Up/Pull Down	60
7 Electrical Specifications	61
7.1 Power and Ground Lands	61
7.2 Decoupling Guidelines	61
7.2.1 Voltage Rail Decoupling	61
7.3 Processor Clocking (BCLK[0], BCLK#[0])	62
7.3.1 PLL Power Supply	62
7.4 VCC Voltage Identification (VID)	62
7.5 Reserved or Unused Signals	66
7.6 Signal Groups	66
7.7 Test Access Port (TAP) Connection	69
7.8 Absolute Maximum and Minimum Ratings	69
7.9 DC Specifications	70
7.9.1 Voltage and Current Specifications	70
7.10 Platform Environmental Control Interface (PECI) DC Specifications	77
7.10.1 DC Characteristics	77
7.10.2 Input Device Hysteresis	78
8 Processor Land and Signal Information	79

Match case Limit results 1 per page

Datasheet, Volume 1

Processor Land and Signal Information

VCC

D35

PWR

VCC

D36

PWR

VCC

D38

PWR

VCC

D39

PWR

VCC

E22

PWR

VCC

E23

PWR

VCC

E25

PWR

VCC

E26

PWR

VCC

E28

PWR

VCC

E29

PWR

VCC

E31

PWR

VCC

E32

PWR

VCC

E34

PWR

VCC

E35

PWR

VCC

E37

PWR

VCC

E38

PWR

VCC

E40

PWR

VCC

F21

PWR

VCC

F22

PWR

VCC

F24

PWR

VCC

F25

PWR

VCC

F27

PWR

VCC

F28

PWR

VCC

F30

PWR

VCC

F31

PWR

VCC

F33

PWR

VCC

F34

PWR

VCC

F36

PWR

VCC

F37

PWR

VCC

F39

PWR

VCC

F40

PWR

VCC

G20

PWR

VCC

G21

PWR

VCC

G23

PWR

VCC

G24

PWR

VCC

G26

PWR

VCC

G27

PWR

VCC

G29

PWR

VCC

G30

PWR

VCC

G32

PWR

VCC

G33

PWR

VCC

G35

PWR

VCC

G36

PWR

VCC

G38

PWR

Table 8-2.

Processor Pin List by Pin

Name

Pin Name

Pin #

Buffer Type

Dir.

VCC

G39

PWR

VCC

H19

PWR

VCC

H20

PWR

VCC

H22

PWR

VCC

H23

PWR

VCC

H25

PWR

VCC

H26

PWR

VCC

H28

PWR

VCC

H29

PWR

VCC

H31

PWR

VCC

H32

PWR

VCC

H34

PWR

VCC

H35

PWR

VCC

H37

PWR

VCC

H38

PWR

VCC

H40

PWR

VCC

J18

PWR

VCC

J19

PWR

VCC

J21

PWR

VCC

J22

PWR

VCC

J24

PWR

VCC

J25

PWR

VCC

J27

PWR

VCC

J28

PWR

VCC

J30

PWR

VCC

J31

PWR

VCC

J33

PWR

VCC

J34

PWR

VCC

J36

PWR

VCC

J37

PWR

VCC

J39

PWR

VCC

J40

PWR

VCC

K17

PWR

VCC

K18

PWR

VCC

K20

PWR

VCC

K21

PWR

VCC

K23

PWR

VCC

K24

PWR

VCC

K26

PWR

VCC

K27

PWR

VCC

K29

PWR

VCC

K30

PWR

VCC

K32

PWR

VCC

K33

PWR