Intel BX80605X3430 Data Sheet - Page 53
PCI Express* Based Interface Signals, DMI-Processor to PCH Serial Interface
UPC - 735858210331
View all Intel BX80605X3430 manuals
Add to My Manuals
Save this manual to your list of manuals |
Page 53 highlights
Signal Description Table 6-5. Reset and Miscellaneous Signals (Sheet 2 of 2) Signal Name RESET_OBS# Description This signal is an indication of the processor being reset. Direction O RSTIN# RSVD RSVD_NCTF RSVD_TP SM_DRAMRST# Reset In: When asserted, this signal will asynchronously reset the processor logic. This signal is connected to the I PLTRST# output of the PCH. RESERVED. Must be left unconnected on the board. Intel does not recommend a test point on the board for this land. RESERVED/Non-Critical to Function: Pin for package mechanical reliability. A test point may be placed on the board for this land. RESERVED-Test Point. A test point may be placed on the board for this land. DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One common to all channels. O Type Asynch CMOS CMOS DDR3 6.4 PCI Express* Based Interface Signals Table 6-6. PCI Express* Based Interface Signals Signal Name PEG_ICOMPI PEG_ICOMPO PEG_RBIAS PEG_RCOMPO PEG_RX[15:0] PEG_RX#[15:0] PEG_TX[15:0] PEG_TX#[15:0] Description PCI Express Current Compensation. PCI Express Current Compensation. PCI Express Resistor Bias Control. PCI Express Resistance Compensation. PCI Express Receive Differential Pair. PCI Express Transmit Differential Pair. Direction I I I I I O Type Analog Analog Analog Analog PCI Express PCI Express 6.5 DMI-Processor to PCH Serial Interface Table 6-7. DMI-Processor to PCH Serial Interface Signal Name DMI_RX[3:0] DMI_RX#[3:0] DMI_TX[3:0] DMI_TX#[3:0] Description DMI input from PCH: Direct Media Interface receive differential pair. DMI output to PCH: Direct Media Interface transmit differential pair. Direction I O Type DMI DMI Datasheet, Volume 1 53