Intel P8700 Data Sheet - Page 11

Low Power Features, 2.1 Clock Control and Low-Power States

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Low Power Features 2 2.1 Low Power Features Clock Control and Low-Power States The processor supports low-power states both at the individual core level and the package level for optimal power management. A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel® Enhanced Deeper Sleep and Intel® Deep Power Down Technology low-power states. When both cores coincide in a common core low-power state, the central power management logic ensures the entire processor enters the respective package lowpower state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, P_LVL5,P_LVL6) I/O read to the GMCH. The processor implements two software interfaces for requesting low-power states: MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK register block mapped in the processor's I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does not need to be set up before using the P_LVLx I/O read interface. The sub-state hints used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model specific register (MSR). If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system logic that individual cores should return to the C0 state and the processor should return to the Normal state. Figure 1 shows the core low-power states and Figure 2 shows the package low-power states for the processor. Table 1 maps the core low-power states to package low-power states. Datasheet 11

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Datasheet
11
Low Power Features
2
Low Power Features
2.1
Clock Control and Low-Power States
The processor supports low-power states both at the individual core level and the
package level for optimal power management.
A core may independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, C4, Intel®
Enhanced Deeper Sleep and Intel® Deep Power Down Technology low-power states.
When both cores coincide in a common core low-power state, the central power
management logic ensures the entire processor enters the respective package low-
power state by initiating a P_LVLx (P_LVL2, P_LVL3, P_LVL4, P_LVL5,P_LVL6) I/O read
to the GMCH.
The processor implements two software interfaces for requesting low-power states:
MWAIT instruction extensions with sub-state hints and P_LVLx reads to the ACPI P_BLK
register block mapped in the processor’s I/O address space. The P_LVLx I/O reads are
converted to equivalent MWAIT C-state requests inside the processor and do not
directly result in I/O reads on the processor FSB. The P_LVLx I/O Monitor address does
not need to be set up before using the P_LVLx I/O read interface. The sub-state hints
used for each P_LVLx read can be configured through the IA32_MISC_ENABLES model
specific register (MSR).
If a core encounters a GMCH break event while STPCLK# is asserted, it asserts the
PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to system
logic that individual cores should return to the C0 state and the processor should return
to the Normal state.
Figure 1
shows the core low-power states and
Figure 2
shows the package low-power
states for the processor.
Table 1
maps the core low-power states to package low-power
states.