Intel P8700 Data Sheet - Page 22

Low Power Features

22

Datasheet

NOTES:

1.

All common clock signals will be active for two BCLKs instead of one (e.g., ADS#, HIT#).

2.

The double-pumped signal strobes will have only one transition per BCLK when active,

instead of two.

3.

The quad-pumped signal strobes will have only two transitions per BCLK when active,

instead of four.

4.

Same setup and hold times apply, but relative to every second rising BCLK.

5.

Following a RESET#, the bus will be in the legacy full-frequency mode.

6.

There will not be a down-shift right after RESET# deassertion.

7.

There is no backing out of a transition into or out of half-frequency mode. Once the

sequence starts it must be completed.

2.4.2

Enhanced Intel® Dynamic Acceleration Technology

The processor supports Intel Dynamic Acceleration Technology mode. The Intel

Dynamic Acceleration Technology feature allows one core of the processor to operate at

a higher frequency point when the other core is inactive and the operating system

requests increased performance. This higher frequency is called the opportunistic

frequency and the maximum rated operating frequency is the ensured frequency.

The processor includes a hysteresis mechanism that improves overall Intel Dynamic

Acceleration Technology performance by decreasing unnecessary transitions of the

cores in and out of Intel Dynamic Acceleration Technology mode. Normally, the

processor would exit Intel Dynamic Acceleration Technology as soon as two cores are

active. This can become an issue if the idle core is frequently awakened for a short

periods (i.e., high timer tick rates). The hysteresis mechanism allows two cores to be

active for a limited time before it transitions out of Intel Dynamic Acceleration

Technology mode.

Intel Dynamic Acceleration Technology mode enabling requires:

•

Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state

•

Enhanced Multi-Threaded Thermal Management (EMTTM)

•

Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via

BIOS.

Figure 3.

Dynamic FSB Frequency Switching Protocol

Section	Page
Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Core™2 Extreme Mobile Processor on 45-nm Process	1
Revision History	6
1 Introduction	7
1.1 Terminology	8
1.2 References	9
2 Low Power Features	11
2.1 Clock Control and Low-Power States	11
2.1.1 Core Low-Power State Descriptions	13
2.1.2 Package Low-power State Descriptions	15
2.2 Enhanced Intel SpeedStep® Technology	19
2.3 Extended Low-Power States	20
2.4 FSB Low Power Enhancements	21
2.4.1 Dynamic FSB Frequency Switching	21
2.4.2 Enhanced Intel® Dynamic Acceleration Technology	22
2.5 VID-x	23
2.6 Processor Power Status Indicator (PSI-2) Signal	23
3 Electrical Specifications	25
3.1 Power and Ground Pins	25
3.2 Decoupling Guidelines	25
3.2.1 VCC Decoupling	25
3.2.2 FSB AGTL+ Decoupling	25
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking	25
3.3 Voltage Identification and Power Sequencing	26
3.4 Catastrophic Thermal Protection	29
3.5 Reserved and Unused Pins	29
3.6 FSB Frequency Select Signals (BSEL[2:0])	29
3.7 FSB Signal Groups	30
3.8 CMOS Signals	31
3.9 Maximum Ratings	31
3.10 Processor DC Specifications	32
4 Package Mechanical Specifications and Pin Information	51
4.1 Package Mechanical Specifications	51
4.2 Processor Pinout and Pin List	59
4.3 Alphabetical Signals Reference	93
5 Thermal Specifications and Design Considerations	101
5.1 Monitoring Die Temperature	108
5.1.1 Thermal Diode	108
5.1.2 Intel® Thermal Monitor	109
5.1.3 Digital Thermal Sensor	111
5.2 Out of Specification Detection	112

Intel P8700 Data Sheet - Page 22

Enhanced Intel® Dynamic Acceleration Technology,

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