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Intel P8700 Data Sheet - Page 58

Intel Core 2 Duo Mobile Processor ULV SC and ULV DC Die Micro-FCBGA

UPC - 735858206174

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Datasheet 58 THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION. B1 B (C1) 0.203 A G1 H1 (C2) B2 DIE PACKAGE C (D1) TOP VIEW A SEE DETAIL A FRONT VIEW Die Package Substrate Epoxy Underfill A DETAIL SCALE 45 SIDE VIEW J2 BC BA AW AU AR AN AL AJ AG AE AC AA W U R N L J G E C BD BB AY AV AT AP AM AK AH AF AD AB Y V T P M K H F D AB G2 H2 SEE DETAIL B 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 J1 BOTTOM VIEW F3 F5 A ø0.46±0.04 (Metal Diameter) B DETAIL SCALE 75 BGA LAND 956 PLACES ø0.39±0.02 (Solder Resist Opening) SYMBOL B1 B2 C1 C2 D1 F3 F5 G1 G2 H1 H2 J1 J2 MILLIMETERS MIN MAX 21.95 22.05 21.95 22.05 8.68 9.41 0.926 1.437 1.647 0.205 0.355 20.468 BASIC 20.468 BASIC 10.234 BASIC 10.234 BASIC 0.476 BASIC 0.476 BASIC COMMENTS ø0.14 L A B C ø0.04 L A B6748-01 E38344(1) Package Mechanical Specifications and Pin Information Figure 15. Intel Core 2 Duo Mobile Processor (ULV SC and ULV DC) Die Micro-FCBGA Processor Package Drawing

Section	Page
Intel® Core™2 Duo Mobile Processor, Intel® Core™2 Solo Mobile Processor and Intel® Core™2 Extreme Mobile Processor on 45-nm Process	1
Revision History	6
1 Introduction	7
1.1 Terminology	8
1.2 References	9
2 Low Power Features	11
2.1 Clock Control and Low-Power States	11
2.1.1 Core Low-Power State Descriptions	13
2.1.2 Package Low-power State Descriptions	15
2.2 Enhanced Intel SpeedStep® Technology	19
2.3 Extended Low-Power States	20
2.4 FSB Low Power Enhancements	21
2.4.1 Dynamic FSB Frequency Switching	21
2.4.2 Enhanced Intel® Dynamic Acceleration Technology	22
2.5 VID-x	23
2.6 Processor Power Status Indicator (PSI-2) Signal	23
3 Electrical Specifications	25
3.1 Power and Ground Pins	25
3.2 Decoupling Guidelines	25
3.2.1 VCC Decoupling	25
3.2.2 FSB AGTL+ Decoupling	25
3.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking	25
3.3 Voltage Identification and Power Sequencing	26
3.4 Catastrophic Thermal Protection	29
3.5 Reserved and Unused Pins	29
3.6 FSB Frequency Select Signals (BSEL[2:0])	29
3.7 FSB Signal Groups	30
3.8 CMOS Signals	31
3.9 Maximum Ratings	31
3.10 Processor DC Specifications	32
4 Package Mechanical Specifications and Pin Information	51
4.1 Package Mechanical Specifications	51
4.2 Processor Pinout and Pin List	59
4.3 Alphabetical Signals Reference	93
5 Thermal Specifications and Design Considerations	101
5.1 Monitoring Die Temperature	108
5.1.1 Thermal Diode	108
5.1.2 Intel® Thermal Monitor	109
5.1.3 Digital Thermal Sensor	111
5.2 Out of Specification Detection	112