Intel P8700 Data Sheet - Page 13

Low Power Features Figure 2. Package Low-Power States Normal STPCLK# asserted STPCLK# deasserted Stop Grant SLP# asserted SLP# deasserted Sleep DPSLP# asserted Deep Sleep DPSLP# deasserted DPRSTP# asserted Deeper Sleep† DPRSTP# deasserted Snoop Snoop serviced occurs Stop Grant Snoop † - Deeper Sleep includes the Deeper Sleep state, Deep C4 sub-state, and C6 Table 1. 2.1.1 2.1.1.1 2.1.1.2 Coordination of Core Low-Power States at the Package Level Package State Core1 State Core0 State C0 C11 C2 C3 C4/Deep Power Down Technology C0 Normal Normal Normal Normal Normal C11 C2 C4/Deep Power Down C3 Technology State (Code Named C6 State) Normal Normal Normal Normal Normal Normal Normal Stop-Grant Stop-Grant Stop-Grant Normal Normal Stop-Grant Deep Sleep Deep Sleep Normal Normal Stop-Grant Deep Sleep Deeper Sleep /Intel® Enhanced Deeper Sleep/ Intel® Deep Power Down NOTE: 1. AutoHALT or MWAIT/C1. Core Low-Power State Descriptions Core C0 State This is the normal operating state for cores in the processor. Core C1/AutoHALT Powerdown State C1/AutoHALT is a low-power state entered when a core executes the HALT instruction. The processor core will transition to the C0 state upon occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals, Volume 3A/3B: System Programmer's Guide for more information. Datasheet 13